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Registered: ‎04-03-2017

xdc package_pin make no connection

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I've got a zynq block diagram design that I want to be able to build for two different motherboards.

One of the two motherboards requires that I set a few enable lines to constants.  In the other design, I don't need these outputs.

I want to be able to choose which design to build based on which xdc file I include in the project (everything else is the same).

Is there anyway for me to specify, in an xdc file, that I want to leave an output disconnected (not connected to any pins)?

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Registered: ‎01-22-2015

26DEC19 EDIT:  THIS ANSWER IS WRONG - PLEASE SEE OTHER POSTS IN THIS THREAD FOR POSSIBLE SOLUTIONS

 

@trehcir 

Is there anyway for me to specify, in an xdc file, that I want to leave an output disconnected (not connected to any pins)?

I see from other posts that you are using VHDL for part of your design.  In your Vivado VHDL project, you can simply comment-out the pin constraints (eg. set_property IOSTANDARD, set_property PACKAGE_PIN) from the xdc-file that correspond to unconnected IO in the VHDL top-level component.   -and Vivado should not complain (ie. throw warnings or errors) when you do this.

Mark

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819 Views
Registered: ‎01-22-2015

26DEC19 EDIT:  THIS ANSWER IS WRONG - PLEASE SEE OTHER POSTS IN THIS THREAD FOR POSSIBLE SOLUTIONS

 

@trehcir 

Is there anyway for me to specify, in an xdc file, that I want to leave an output disconnected (not connected to any pins)?

I see from other posts that you are using VHDL for part of your design.  In your Vivado VHDL project, you can simply comment-out the pin constraints (eg. set_property IOSTANDARD, set_property PACKAGE_PIN) from the xdc-file that correspond to unconnected IO in the VHDL top-level component.   -and Vivado should not complain (ie. throw warnings or errors) when you do this.

Mark

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Registered: ‎04-03-2017

I'm using a block design with IP Integrator (which generates a vhdl wrapper).

I get the error message: " Rule violation (NSTD-1) Unspecified I/O Standard:"

"logical ports use I/O standard (IOSTANDARD) value 'DEFAULT', instead of a user assigned specific value. This may cause I/O contention or incompatibility with the board power or connectivity affecting performance, signal integrity or in extreme cases cause damage to the device or the components to which it is connected."

I think all outputs have to be specified, or the NSTD-1 error has to be degraded to a warning in order for the design to build without error.

What am I missing?

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Registered: ‎01-22-2015

@trehcir 

     What am I missing?
You are not missing anything – and I am sorry.  Whether or not you are using block design, my previous reply to you is wrong.  So, please uncheck my previous reply as a solution.

As you say, when you do not have IOSTANDARD and PACKAGE_PIN constraints for IO then Vivado throws an error message which prevents generation of the bitstream.  This error message tells us that we can downgrade the error to a warning – but discourages us from doing this.

Here are a couple of things that should work for you…

If you have an output from your design that is connected to an FPGA pin and the pin is unconnected to anything on the board, then is it fine to simply let it remain that way.  Similarly, an input to your design that connects to a pin which is unconnected to anything on the board can be left as is if you enable a pullup (or pulldown) on the pin.

set_property PULLTYPE PULLUP [get_ports my_input]

Instead of the above method, the IO in question can have two sets of IOSTANDARD and PACKAGE_PIN constraints in the xdc-file.  Use the 1st set of constraints when the IO is being used in your project.  Use the 2nd set of constraints when the IO is not being used.  This second set of constraints assigns the IO to an unused pin on the FPGA (and enables a pullup on the pin if it is an input).

Finally, instead of commenting/uncommenting constraints in a single xdc-file, I recommend using separate xdc-files for your separate designs.  Ask Vivado to disable the xdc-files that you are not using.

Mark

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