编译错误 vivado 12-1411

[xumoxiao]

麻烦帮忙看看这是啥问题。貌似共用了同一个资源 GTHE4_CHANNEL

[Vivado 12-1411] Cannot set LOC property of ports, Instance

u_sys_wrapper/sys_i/xdma_1/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/sys_xdma_1_0_pcie4_ip_gt_i/inst
/gen_gtwizard_gthe4_top.sys_xdma_1_0_pcie4_ip_gt_gtwizard_gthe4_inst/gen_gtwizard_gthe4.gen_channel_container[0].
gen_enabled_channel.gthe4_channel_wrapper_inst/channel_inst/gthe4_channel_gen.gen_gthe4_channel_inst[0].GTHE4_CHANNEL_PRIM_INST

can not be placed in GTHE4_CHANNEL of site GTHE4_CHANNEL_X0Y3 because the bel is occupied by

u_zu_arr/CB[0].u_v7_arr_to_cb_wp/u_arr_wp/u_arr_6466_x4_wp/u_aurora_6466_support/aurora_64b66b_0_i/inst/aurora_64b66b_wrapper_i/aurora_64b66b_multi_gt_i
/aurora_64b66b_gt_i/inst/gen_gtwizard_gthe4_top.aurora_64b66b_gt_gtwizard_gthe4_inst/gen_gtwizard_gthe4.gen_channel_container[0].
gen_enabled_channel.gthe4_channel_wrapper_inst/channel_inst/gthe4_channel_gen.gen_gthe4_channel_inst[3].GTHE4_CHANNEL_PRIM_INST(port:).
This could be caused by bel constraint conflict ["E:/0035zu_ImgHub/src/constrs/zu_image_hub.tcl":328]

我是在 zu11eg 上进行开发

需要用 3个xdma Gen3 lane x 4 和 6个aurora6466 lane x 4

3个xdma 的工程单独编译没有问题， 6个aurora 的工程单独编译没有问题。合在一起后布局布线报错（不是警告）。

这个是什么原因？我在论坛中查过。说是可以把 IBUFDS_GTE4 替换为  IBUFDS 。

但是xdma 是gen3 的好像必须要用IBUFDS_GTE4 做一个分频。所以我将aurora6466的时钟修改为  IBUFDS 。

布局布线依然报错，更多了一些警告。

[Vivado 12-2285] Cannot set LOC property of instance 'u_zu_arr/CB[1].u_v7_arr_to_cb_wp/u_arr_wp/u_arr_6466_x4_wp/u_aurora_6466_support/aurora_64b66b_0_i/inst/aurora_64b66b_wrapper_i/aurora_64b66b_multi_gt_i/aurora_64b66b_gt_i/inst/gen_gtwizard_gthe4_top.aurora_64b66b_gt_gtwizard_gthe4_inst/gen_gtwizard_gthe4.gen_channel_container[0].gen_enabled_channel.gthe4_channel_wrapper_inst/channel_inst/gthe4_channel_gen.gen_gthe4_channel_inst[0].GTHE4_CHANNEL_PRIM_INST'... Instance u_zu_arr/CB[1].u_v7_arr_to_cb_wp/u_arr_wp/u_arr_6466_x4_wp/u_aurora_6466_support/aurora_64b66b_0_i/inst/aurora_64b66b_wrapper_i/aurora_64b66b_multi_gt_i/aurora_64b66b_gt_i/inst/gen_gtwizard_gthe4_top.aurora_64b66b_gt_gtwizard_gthe4_inst/gen_gtwizard_gthe4.gen_channel_container[0].gen_enabled_channel.gthe4_channel_wrapper_inst/channel_inst/gthe4_channel_gen.gen_gthe4_channel_inst[0].GTHE4_CHANNEL_PRIM_INST can not be placed in GTHE4_CHANNEL of site GTHE4_CHANNEL_X0Y0 because the bel is occupied by u_zu_arr/CB[0].u_v7_arr_to_cb_wp/u_arr_wp/u_arr_6466_x4_wp/u_aurora_6466_support/aurora_64b66b_0_i/inst/aurora_64b66b_wrapper_i/aurora_64b66b_multi_gt_i/aurora_64b66b_gt_i/inst/gen_gtwizard_gthe4_top.aurora_64b66b_gt_gtwizard_gthe4_inst/gen_gtwizard_gthe4.gen_channel_container[0].gen_enabled_channel.gthe4_channel_wrapper_inst/channel_inst/gthe4_channel_gen.gen_gthe4_channel_inst[0].GTHE4_CHANNEL_PRIM_INST(port:). This could be caused by bel constraint conflict ["e:/0035zu_ImgHub/src/ip/aurora_64b66b/ip_0/synth/aurora_64b66b_gt.xdc":57]

请问是什么原因，该如何处理？

[graces]

典型的原因是IP自带的约束文件里有GT的位置约束，如果多个IP的约束文件里均带有同样的位置约束，就会产生冲突。

以这个错误为例，

[Vivado 12-2285] Cannot set LOC property of instance 'u_zu_arr/CB[1].u_v7_arr_to_cb_wp/u_arr_wp/u_arr_6466_x4_wp/u_aurora_6466_support/aurora_64b66b_0_i/inst/aurora_64b66b_wrapper_i/aurora_64b66b_multi_gt_i/aurora_64b66b_gt_i/inst/gen_gtwizard_gthe4_top.aurora_64b66b_gt_gtwizard_gthe4_inst/gen_gtwizard_gthe4.gen_channel_container[0].gen_enabled_channel.gthe4_channel_wrapper_inst/channel_inst/gthe4_channel_gen.gen_gthe4_channel_inst[0].GTHE4_CHANNEL_PRIM_INST'... Instance u_zu_arr/CB[1].u_v7_arr_to_cb_wp/u_arr_wp/u_arr_6466_x4_wp/u_aurora_6466_support/aurora_64b66b_0_i/inst/aurora_64b66b_wrapper_i/aurora_64b66b_multi_gt_i/aurora_64b66b_gt_i/inst/gen_gtwizard_gthe4_top.aurora_64b66b_gt_gtwizard_gthe4_inst/gen_gtwizard_gthe4.gen_channel_container[0].gen_enabled_channel.gthe4_channel_wrapper_inst/channel_inst/gthe4_channel_gen.gen_gthe4_channel_inst[0].GTHE4_CHANNEL_PRIM_INST can not be placed in GTHE4_CHANNEL of site GTHE4_CHANNEL_X0Y0 because the bel is occupied by u_zu_arr/CB[0].u_v7_arr_to_cb_wp/u_arr_wp/u_arr_6466_x4_wp/u_aurora_6466_support/aurora_64b66b_0_i/inst/aurora_64b66b_wrapper_i/aurora_64b66b_multi_gt_i/aurora_64b66b_gt_i/inst/gen_gtwizard_gthe4_top.aurora_64b66b_gt_gtwizard_gthe4_inst/gen_gtwizard_gthe4.gen_channel_container[0].gen_enabled_channel.gthe4_channel_wrapper_inst/channel_inst/gthe4_channel_gen.gen_gthe4_channel_inst[0].GTHE4_CHANNEL_PRIM_INST(port:). This could be caused by bel constraint conflict ["e:/0035zu_ImgHub/src/ip/aurora_64b66b/ip_0/synth/aurora_64b66b_gt.xdc":57]

你可以找到信息中提示的IP XDC文件，e:/0035zu_ImgHub/src/ip/aurora_64b66b/ip_0/synth/aurora_64b66b_gt.xdc，第57行应该是将cell约束到GTHE4_CHANNEL_X0Y0的set_property LOC命令。

同样地，其他IP也会包含此约束文件，比如e:/0035zu_ImgHub/src/ip/aurora_64b66b/ip_1/synth/aurora_64b66b_gt.xdc，文件中包含相同的约束，由此冲突了。

对这类例化多个IP可能存在GT位置冲突的情况，建议在顶层的用户XDC中做正确的位置约束。

[xumoxiao]

这个我理解，但是很奇怪，位置不应该有冲突。

我的xdma 在blockdesign 中进行位置设定bank224

那一组aurora6466 在外部tcl顶层约束中使用bank231 通过管脚约束完成。

####qsfp 231
create_clock -period 8.000 [get_ports {i_gt_refclk_p[1]}]
set_property PACKAGE_PIN M4 [get_ports {rxp[4]}]
set_property PACKAGE_PIN L2 [get_ports {rxp[5]}]
set_property PACKAGE_PIN J2 [get_ports {rxp[6]}]
set_property PACKAGE_PIN G2 [get_ports {rxp[7]}]
set_property PACKAGE_PIN T12 [get_ports {i_gt_refclk_p[1]}]

但是任然会报

[Vivado 12-1411] Cannot set LOC property of ports, Instance

u_sys_wrapper/sys_i/xdma_1/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/sys_xdma_1_0_pcie4_ip_gt_i/inst
/gen_gtwizard_gthe4_top.sys_xdma_1_0_pcie4_ip_gt_gtwizard_gthe4_inst/gen_gtwizard_gthe4.gen_channel_container[0].
gen_enabled_channel.gthe4_channel_wrapper_inst/channel_inst/gthe4_channel_gen.gen_gthe4_channel_inst[0].GTHE4_CHANNEL_PRIM_INST

can not be placed in GTHE4_CHANNEL of site GTHE4_CHANNEL_X0Y3 because the bel is occupied by

u_zu_arr/CB[0].u_v7_arr_to_cb_wp/u_arr_wp/u_arr_6466_x4_wp/u_aurora_6466_support/aurora_64b66b_0_i/inst/aurora_64b66b_wrapper_i/aurora_64b66b_multi_gt_i
/aurora_64b66b_gt_i/inst/gen_gtwizard_gthe4_top.aurora_64b66b_gt_gtwizard_gthe4_inst/gen_gtwizard_gthe4.gen_channel_container[0].
gen_enabled_channel.gthe4_channel_wrapper_inst/channel_inst/gthe4_channel_gen.gen_gthe4_channel_inst[3].GTHE4_CHANNEL_PRIM_INST(port:).
This could be caused by bel constraint conflict ["E:/0035zu_ImgHub/src/constrs/zu_image_hub.tcl":328]

到底是什么资源冲突了？

GTHE4_CHANNEL每个quad独立的四个，这两个IP用的是不同的quad不可能重叠。

[hongh]

IBUFDS_GTE4 是用于GT reference clock的专用buffer， 不应该替换成IBUFDS.

你的顶层和底层IP 的LOC约束有冲突的话， 建议在place之前（TCL.PRE placer属性）reset 掉设计中IP自带的GT_CHANNEL 的LOC约束再加你希望加的LOC约束.

建议直接约GT的LOC，这样比较直观.

Example tcl:

reset_property LOC [get_cells -hier -filter [REF_NAME =~ GTHE4_CHANNEL*]]

set_property LOC XX [get_cells GT_XX]

....

[xumoxiao]

我用简单的方式，将aurora 6466b IP中的aurora_64b66b_gt.xdc约束给注释掉了
#set_property LOC GTHE4_CHANNEL_X0Y1 [get_cells -hierarchical -filter {NAME =~ *gen_channel_container[0].*gen_gthe4_channel_inst[1].GTHE4_CHANNEL_PRIM_INST}]

布局布线以及生成bit 文件都成功了。
想请问有没有什么方式 可以防止vivado 通过xci生成IP的时候重新覆盖我修改的IP内部约束呢?
麻烦指导以下炒作流程。

[hongh · Accepted solution]

Hi, @xumoxiao ,

可以尝试两个方法:

1. 直接disable 掉IP的位置约束相关的XDC, 其他需要的约束可以转到顶层的XDC中.

2 使用之前提到的reset_property LOC 的命令清除IP自带的LOC位置的影响.

[xumoxiao]

好的！感谢！

[xumoxiao]

我现在想用 reset_property LOC为啥都报错呢？
reset_property LOC [get_cells -hier -filter {REF_NAME =~ *GT }]

reset_property LOC GTYE4_CHANNEL_X0Y4 [get_cells -hierarchical -filter {NAME =~ *gen_channel_container[1].*gen_gtye4_channel_inst[0].GTYE4_CHANNEL_PRIM_INST}]
以上两句都分别试过，都会报错
[Common 17-161] Invalid option value 'GTYE4_CHANNEL_X0Y4' specified for 'objects'. ["E:/0035zu_ImgHub/src/constrs/zu_sub_x8_test.tcl":2]

[xumoxiao]

block design 中的IP约束 disable不了呀？怎么办？

[hongh]

Hi, @xumoxiao ,

使用第二个方法，用reset_property LOC [get_cells XX] 命令来清除不需要的位置约束