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Visitor
Visitor
608 次查看
注册日期: ‎11-16-2020

LUT的对称布局

jhc3601212_1-1606295901758.png

1.这种LUT内外嵌套,B5LUT和B6LUT实际上是同一个LUT,还是说他们是两个分别的LUT?

2.为什么我在手动布局的时候有的橘黄色块只能放在里面的LUT里,而有的橘黄色块只能放在外面那一层LUT里?

3.如果A5LUT A6LUT是分别不同的两个LUT,那么我把两个橘黄色块分别放在A5LUT 和A6LUT里,那么从别的模块发来一个信号同时施加给A5LUT和A6LUT,那么这个信号到达A5LUT和A6LUT的时延是相同的吗(换句话说这两个LUT的布局是对称布局吗)

 

 

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Teacher
Teacher
596 次查看
注册日期: ‎07-09-2009

I can answer (3)
the delay is is only guaranteed within the range specified in the datasheet.
Its unlikely that tow LUTs next to each other are that different, but no guarantee.

Why are you manually placing ?
is this for some sort of oscillator circuit ?
manual placing is fighting the tools, so you are going to always have a hard time compared to using constraints.


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Xilinx Employee
Xilinx Employee
591 次查看
注册日期: ‎02-28-2019

这个更偏向于架构的。

它们一个LUT,它可以根据情况,一种是6输入1输出的,另一种是5(或更少)输入2输出的,不用的那个输入置高。简单的来说,取决于你使用LUT的规模大小,如果是简单的,那它就会是您看到的内部LUT(小)。如果是很复杂的,需要一个大LUT,那就是您看到的外部LUT(大)。

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Visitor
Visitor
588 次查看
注册日期: ‎11-16-2020

1.但是情况是我正在使用的这些LUT基本都是简单的反相器,他们按理说都是对称的,缺出现有的反相器是外层大的LUT,有的反相器是内层小的LUT。这是为什么呢?

2.内层和外层的LUT会造成不同的时延吗,我需要两路对称的path(每条path都是一串反相器和mux的串联)

jhc3601212_0-1606297678019.png

 

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Teacher
Teacher
584 次查看
注册日期: ‎07-09-2009

Its physically impossible to guarantee both paths have the same delay,

I'm dying to know what this is for though
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Visitor
Visitor
583 次查看
注册日期: ‎11-16-2020

jhc3601212_0-1606297791817.png

 

I am implementing two symmetric paths. I need the two paths' delay time to be same. So I am manually placing them. At least making them structurally symmetric. The internal delay time variance is what I want!

 

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Visitor
Visitor
580 次查看
注册日期: ‎11-16-2020

The two paths internal delay time variance let the signals arrive at the arbiter randomly sequential. So the arbiter can give the random 1/0. The random 1/0 is what I want. To make the randomness, the two paths need to be structrually symmetric.
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Teacher
Teacher
556 次查看
注册日期: ‎07-09-2009

Thank you

what an interesting idea,
multiple random ring oscillators have been most common method I have seen on the forums so far. They have the same issue of fighting the tools, manual placing and delay calculation.

This might be of use to find references

https://forums.xilinx.com/t5/Other-FPGA-Architecture/How-to-implement-a-ring-oscillator-with-routings-of-FPGA-Where/td-p/768444



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Visitor
Visitor
457 次查看
注册日期: ‎11-16-2020

Thanks a lot.

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Moderator
Moderator
443 次查看
注册日期: ‎11-05-2010

Hi, @jhc3601212 

采用以下的命令可以控制让LUT输出使用O5(LUT5) 或者O6(LUT6):

place_cell {clkx_nsamp_i0/bus_new_cnt_src[0]_i_1} SLICE_X7Y218/A5LUT

place_cell {clkx_nsamp_i0/bus_new_cnt_src[0]_i_1} SLICE_X7Y218/A6LUT

信号到达O5和O6的时延有细微的差异,一般来说从O6输出的时延会比O5输出小

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Visitor
Visitor
434 次查看
注册日期: ‎11-16-2020

好的,我试试命令.

但是发现用鼠标拖动一个lut,有的lut只能被拖到某些空白lut,而不能放入另一些空白lut,系统会限定我只能将某一个lut拖入系统指定的一些空白lut.而我希望拖到的位置应该是可以让我的两条path中的同一级的两个反相器对称的位置。例如我截图的上下两个LUT的位置应该是对称的吧?(对称也即我希望上下两条路径延时对称)

如果我希望得到两条对称的lut,那按您所说要做到所有反相器要都放入外层lut,或者都放入内层lut对吧。

 

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Moderator
Moderator
428 次查看
注册日期: ‎11-05-2010

都放外层或者内层,内部延迟会更接近,但是布线的差异也也能引入一部分差异【外层内层只是显示的差异.】

你有放不了的LUT可以提供DCP文件,这里可以帮你一起找下原因

 

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Visitor
Visitor
416 次查看
注册日期: ‎11-16-2020

你提到说内层外层只是显示的差异,但是我可以将一个反相器放在内层,另一个反相器放在外层,这说明他们应该是不同的LUT吧

jhc3601212_1-1606368334458.png

如图,这个内层和外层放置了两个不同的反相器形成的LUT 内层是path2的第23个反相器,外层是path1的第22个反相器,这两个反相器分别放在了内外两个LUT里,如果说内外只是显示的差异(即内外层LUT是同一个LUT),那么应该两个不同的反相器不能放到同一个LUT里面吧。我的代码将不同的反相器全都禁止优化,他们是分开的。

jhc3601212_3-1606368562577.png

 

 

 

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Moderator
Moderator
374 次查看
注册日期: ‎11-05-2010

内层外层的两个反相器(LUT1)实际用的是同一个LUT6的资源. 你可看下UG574 的“Look-Up Table”部分.

 

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LUT6.png