你好，我的设计中想生成一个三个端口的RAM，用BRAM实现。PortA可以读写，PortB只可以写，PortC只可以读。我按照RAM coding guidlines中的介绍进行设计，并且添加了综合指导(*ram_style = "block" *),但是综合出来是以LUT的形式出现，report中出现mem won't be mapped to RAM because it is too sparse
下面是我的代码，我想问下是否可以让mem综合成调用BRAM资源
module two_port_ram(
input hclk,
input ena,
input enb,
input enc,
input wena,//read/write
//input wenb,//just for write
input [ADDRWIDTH-1:0]addra,
input [ADDRWIDTH-1:0]addrb,
input [ADDRWIDTH-1:0]addrc,
input [31:0]dina,
input [31:0]dinb,
output reg [31:0] doa,
//output reg [31:0] dob,//for write
output reg [31:0] doc,// for read
output softmax_start
);
parameter ADDRWIDTH = 6;
parameter MEMDEPTH = 2**(ADDRWIDTH);
(*ram_style = "block" *)reg [31:0] mem[MEMDEPTH-1:0];
assign softmax_start = (mem[0] == 32'hffff000);
//portA for ahb read/write
always@(posedge hclk)begin
if(ena)begin
if(wena)
mem[addra] <= dina;
doa <= mem[addra];
end
end
//portB for softmax write only
always@(posedge hclk)begin
if(enb)begin
mem[addrb] <= dinb;
end
end
//portC for softmax read only
always@(posedge hclk)begin
if(enc)
doc <= mem[addrc];
end
endmodule
