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Visitor
Visitor
544 次查看
注册日期: ‎07-31-2020

selectio refclk问题

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我用selectio 做lvds 接口处理,lvds接口的差分时钟是245.76Mhz, 而我送进selectio的refclk也是245.76Mhz, 看了selectio里refclk是给idelayctrl 用,收到critial warning说idelayctrl 的时钟和idelay2_bus的时钟不一致,idelay2_bus是Default 200Mhz, 这里这个critial warning会有影响吗?

idelayctrl 的时钟和idelay2_bus的时钟是要求必须一致吗? 这个refclk与lvds的差分时钟有没有联系?

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Xilinx Employee
Xilinx Employee
473 次查看
注册日期: ‎02-28-2019

这个refclk与lvds的差分时钟有没有联系?

没有关系,那个reclk的用于idelay tap延时的参考时钟,跟进入FPGA的随路时钟不是一回事。

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Xilinx Employee
Xilinx Employee
474 次查看
注册日期: ‎02-28-2019

这个refclk与lvds的差分时钟有没有联系?

没有关系,那个reclk的用于idelay tap延时的参考时钟,跟进入FPGA的随路时钟不是一回事。

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Don't forget to reply, kudo, and accept as solution.
-------------------------------------------------------------------------

在原帖中查看解决方案

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456 次查看
注册日期: ‎01-22-2015

@zuoliyu 

The SelectIO usually wants you to send a 200MHz clock to port, ref_clock, for use by IDELAYCTRL.  You must generate ref_clock elsewhere in your design and it need not be related to your LVDS interface clock of 245.76MHz.

 

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Moderator
Moderator
448 次查看
注册日期: ‎11-05-2010

Hi, @zuoliyu ,

用的是什么器件? 能否贴出critical warning  的完整信息?

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Visitor
Visitor
395 次查看
注册日期: ‎07-31-2020

非常感谢您的回复!

我这里再多说一句,是不是这里的refclk只是作用于IDELAY 的data tap, 也就是作数据同步, 而这个refclk只与调整的分辨率有关,所以和lvds随路时钟没有关系,不知道我这么理解得对不对。

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392 次查看
注册日期: ‎01-22-2015

Yes, you understand correctly.  ref_clock is not related to the lvds clock

ref_clock must use very special frequency.  Typically, it is 200MHz.   You can try 200MHz and Vivado warnings will tell you if another frequency for ref_clock is needed.

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Visitor
Visitor
376 次查看
注册日期: ‎07-31-2020

Thank you very much for your reply!

Yes you are right!  I have found that refclk was really special and was only allowed to set 190-210Mhz, 290-310Mhz, 390-410Mhz.  It should only related to the resolution of the IDELAY.

Thanks again! Thanks for your patient explanation!

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