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Explorer
Explorer
195 次查看
注册日期: ‎02-14-2019

vivado 综合后的原理图中实线与虚线的区别

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vivado 综合后,打开原理图中,LUT输入有的是实线,有的虚线,实线和虚线的区别是?

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Xilinx Employee
Xilinx Employee
192 次查看
注册日期: ‎07-17-2008

Dotted lines indicate that the net is connected to additional logic that is not displayed in the schematic.

实现表示此信号的负载仅有图上所显示的连接,虚线表示还有其他负载,双击虚线可以进一步展开。

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Highlighted
Xilinx Employee
Xilinx Employee
193 次查看
注册日期: ‎07-17-2008

Dotted lines indicate that the net is connected to additional logic that is not displayed in the schematic.

实现表示此信号的负载仅有图上所显示的连接,虚线表示还有其他负载,双击虚线可以进一步展开。

-------------------------------------------------------------------------
Don't forget to reply, kudo, and accept as solution.
-------------------------------------------------------------------------

在原帖中查看解决方案