vivado17.4与Modelsim10.5的联调仿真问题

[LiangWS]

vivado17.4联调modelsim10.5编译库之后提示了上图所示错误。尝试检查生成库中已存在modelsim.ini文件；也添加了环境变量依旧是不成功

***********************************************************************************************************************
* Library | Language | Mapped Library Name | Error(s) | Warning(s) *
*---------------------------------------------------------------------------------------------------------------------*
* xdma_v4_0_1 | verilog | xdma_v4_0_1 | 1 | 62 *
*---------------------------------------------------------------------------------------------------------------------*
* ldpc_v1_0_1 | verilog | ldpc_v1_0_1 | 1 | 1 *
*---------------------------------------------------------------------------------------------------------------------*

ERROR: [Vivado 12-5602] compile_simlib failed to compile for modelsim with error in 2 libraries (cxl_error.log)
compile_simlib: Time (s): cpu = 00:01:48 ; elapsed = 00:15:21 . Memory (MB): peak = 1372.855 ; gain = 0.000
ERROR: [Common 17-39] 'compile_simlib' failed due to earlier errors.

[hongh · Accepted solution]

根据UG973(v2017.4)，匹配的Modelsim版本是10.6b 

[LiangWS]

好的好的，十分感谢