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Voyager
Voyager
4,546 Views
Registered: ‎04-11-2016

7 Series Transceiver

Hi,

I am trying to understand 7 series Transceiver for Kintex xc7k325tffg900-2 FPGA.

https://www.xilinx.com/support/documentation/user_guides/ug476_7Series_Transceivers.pdf

 

In my project i would like to use configuration as in attachment.

 

In the project LMH1983 

http://www.ti.com/lit/ds/symlink/lmh1983.pdf

has been used which generate 3 clocks. 148.5 MHz, 148.35 MHz and 27 MHz.

 

Similarly Si5324

https://www.silabs.com/Support%20Documents/TechnicalDocs/Si5324.pdf

has been used which generates 156.25 MHz clock and controlled by I2C bus. 

 

148.5 MHz clock from LMH1983 goes to gtxe2_i(GTXE2_COMMON) and 148.35 MHz from  LMH1983 goes to gtxe2_i(GTXE2_CHANNEL) of Transceiver. This is for SDI.

 

27 MHZ clock from LMH1983 goes into a process which controls I2C bus and generates 156.25 MHz clock from Si5324.This 156.25 MHz clock goes into another Transceiver. This is for 10 Gig pcspma.

 

I am trying to understand these clocks and Transceiver relation and how they are arranged and unfortunately have no success.

 

I would like to know could anybody please calrify me the main steps which should be followed to use 7 Series Transceiver in a project. Ug476 seems to me as an Ocean and difficult to understand. It would be great if somebody clarify the concept.

 

transceiver.jpg
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Explorer
Explorer
4,526 Views
Registered: ‎10-14-2015

Hi @fpgalearner

 

Please refer first  Figure 3-28 and Figure 4-22 UG476 for TX and RX GT clock distribution and Transceiver Channel connection.

Then you can see details channel and clock topology topology .Also refer PG168 for a reference

 

https://www.xilinx.com/support/documentation/ip_documentation/gtwizard/v3_1/pg168-gtwizard.pdf

 

Thanks,

Sarada

 

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Voyager
Voyager
4,500 Views
Registered: ‎04-11-2016

Hi @saradapr

thanks for the info but its not seems to be sufficient for my knowledge. Could you please describe little more?

 

one more question:

is there anyway to debug Transceiver more likely data pins(txn, txp, rxn, rxp). vivado doesn't show any option for marking to debug.

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Explorer
Explorer
4,483 Views
Registered: ‎10-14-2015

Hi @fpgalearner,

 

Yes you pull out the  RXN_IN/RXP_IN and TXN_OUT/TXP_OUT port to the Top leave while configure the transceiver IP .

Please refer Port Descriptions in page 14 of PG168

https://www.xilinx.com/support/documentation/ip_documentation/gtwizard/v3_1/pg168-gtwizard.pdf

 

Thanks,

Sarada

 

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Teacher
Teacher
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Registered: ‎03-31-2012

@fpgalearner you cannot mark the differential signals as debug. These are high speed analog signals generated by the transceiver and can only be observed at the IO pins. You should add debug support to the inside facing portion of the transceivers and view the state there (including how you drive them, if all transactions are accepted, the status of the transceivers ie if link is established etc.)

 

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Voyager
Voyager
4,462 Views
Registered: ‎04-11-2016

Hi @muzaffer and @saradapr 

 

I didn't understand I/O Planning (pin configuration) for transceiver.

 

I am using following reference design in kc705 evaluation board:

https://www.xilinx.com/support/documentation/application_notes/xapp592-smpte-sdi-w-k7-gtx-transceivers.pdf

 

and here is the schematic of  SDI transceiver pins(page 9, bank 118 ) of evaluation board connected to FPGA:

https://www.xilinx.com/support/documentation/boards_and_kits/kc705_Schematic_xtp132_rev1_1.pdf

 

Referring to page 9, bank 118 of above link, the funny thing for me is:

In xdc file I can assign any C2M(Carrier to Mezanine) pins as tx and any M2C(Mezanine to Carrier) as rx.

for e.g.

set_property PACKAGE_PIN D2 [get_ports FMC_HPC_DP0_C2M_P]

 

but when I look in I/O planning after opening synthesized design, the corresponding tx and rx pins automatically assigned regardless of what is in xdc file. I mean if tx is from DP0, rx automatically assgins from DP0. and also there is only _P pin and not _N pin in I/O Planning. I manually try to assign direct in I/O planning but there it is also not possible to assign different pins. I mean lets say tx from DP0 and rx from DP2. How to do that?

 

If I take corresponding tx and rx pins, the design works but I want to have different tx and  rx. what has to change?

 

PS:  DP0 -> FMC_HPC_DP0_C2M_P / FMC_HPC_DP0_M2C_P

 

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Teacher
Teacher
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Registered: ‎03-31-2012

@fpgalearner the transceivers have dedicated and fixed IO pins so MGTXTXP0 is fixed to D2 and also pin D2 is fixed on the PCB to be connecting to the net FMC_HPC_DP0_C2M_P which is connected to a fixed pin on the FMC connector. None of these connectivity is negotiable.

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Voyager
Voyager
4,424 Views
Registered: ‎04-11-2016

Hi @muzaffer

Then what should I do when I want to have input(RX) from one SDI Channel let's say DP0 and want to forward/route this RX to another SDI channel let's say DP2 as output(TX)? How to manage pin configuration of transceiver then?

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