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Adventurer
Adventurer
9,263 Views
Registered: ‎03-31-2014

AXI interconnect problem

Hi,

 

I am using a AXI interconnect to connect Master AXI(Created using create and package IP) to Slave AXI of AXI memory mapped PCIe. 

 

MAster AXI sends write address and the ready is asserted. However, write data' valid is asserted but the ready is not asserted. When I debugged in the wave window, AXI interconnect slave  receives the write valid, but does not send ready.

 

I also notice that there is no transactions at the Master of AXI interconnect.

 

Plesae suggest what could be the problem

 

i am using all IP blocks generated by XIlinx Vivado only.

 

Thanks,

Aj

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Observer
Observer
9,254 Views
Registered: ‎03-15-2016

From above I am not sure, whether slave accepts the new address (see the picture 2nd and 3rd line). Uploading the design and waveform could help. Also, try different addresses where master writes the data.

 

AXI.JPG

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Adventurer
Adventurer
9,099 Views
Registered: ‎03-31-2014

@martin336

 

Thanks for the response.

There were two problems. 1. reset and other is the slave address

 

Now it is resolved.

 

 

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