04-08-2016 05:17 AM
I am using a AXI interconnect to connect Master AXI(Created using create and package IP) to Slave AXI of AXI memory mapped PCIe.
MAster AXI sends write address and the ready is asserted. However, write data' valid is asserted but the ready is not asserted. When I debugged in the wave window, AXI interconnect slave receives the write valid, but does not send ready.
I also notice that there is no transactions at the Master of AXI interconnect.
Plesae suggest what could be the problem
i am using all IP blocks generated by XIlinx Vivado only.
04-08-2016 06:41 AM
From above I am not sure, whether slave accepts the new address (see the picture 2nd and 3rd line). Uploading the design and waveform could help. Also, try different addresses where master writes the data.