01-19-2015 10:56 PM
Good afternoon all,
Am planning to configure an target cpld board using IO pins of master fpga board means i.e. like daisy chain. I connecting JTAG header of cpld by using IO pins of master fpga board.
How to program an IO pin of master fpga to configure an target cpld?
Please send any document related to this....
01-19-2015 11:38 PM
Daisy chain uses JTAG pins of both FPGA and CPLD but not IO pins of master fpga.
What are the FPGA and CPLD device part numbers?