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vimalab
Explorer
Explorer
1,659 Views
Registered: ‎10-14-2014

About IO pins programmimg

Good afternoon all,

 

Am planning to configure an target cpld board using IO pins of master fpga board means i.e. like daisy chain.  I connecting JTAG header of cpld by using IO pins of master fpga board.

 

How to program an IO pin of master fpga to configure an target cpld?

 

Please send any document related to this....

 

Thank you

 

Regards

Vimala

 

 

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2 Replies
umamahe
Xilinx Employee
Xilinx Employee
1,648 Views
Registered: ‎08-01-2012

Daisy chain uses JTAG pins of both FPGA and CPLD but not IO pins of master fpga.

 

What are the FPGA and CPLD device part numbers?

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vimalab
Explorer
Explorer
1,640 Views
Registered: ‎10-14-2014

Am using Spartan 3an fpga board (xc3s50antqg144) and xc9572xl cpld board.

 

Regards

Vimala

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