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Registered: ‎06-07-2017

About asynchronous reset - Simulating a Zynq based design without BFM license

Good Folks,

 

My problem is as follows:

 

Context:

I have a zynq based design that interfaces with a radio transceiver card which is essentially a DAC/ADC interface.

 

Since I do NOT have the BFM license and am not able to purchase one at this point, I wrote my own synthesizeable AXI transactors to interface with the IP/custom RTL on the FPGA for simulation purposes.

 

What I don't understand:

I'm having a bit of trouble planning my reset logic. Specifically, when this design runs on h/w the PS provides both clock and reset. To substitute for this I am providing both CLOCK and an asynchronous RESETN s/g from my testbench as input to a 'system top' module which instantiates a 'system wrapper'.

 

With this setup my functional simulation works well and I can see expected results. I wanted to take this further and do a timing simulation.

 

At this point I am able to constraint the CLOCK input to be placed on the Y9 pin which is a clock capable pin on my Zedboard dev. board. This takes care of the clock routing as  far as the place/route goes.

 

 

 

What I understand:

That there's the GSR that is automatically asserted and I have referred to XAPP199 to write the GSR in my testbench. This GSR OR's with my own asynch resetn stimulus automatically.

 

I also understand that the resetn input to every FF in the fpga should be synchronously de-asserted to the associated clock domain and I have done that as well.

 

Question:

 

1. How exactly would I constraint the resetn stimulus that is also an input to the 'system top' module?

Should I simply be using one of the I/O capable pins of the FPGA since I can't see that there's specifically a RESET capable pin that is NOT connected to the PS itself. Would I also then need an 'input delay' constraint?

 

My concern is that both the CLOCK and RESETN pins don't really mimic the actual hardware setup where there'd be a PS sourcing the CLOCK and RESET logic directly to the FPGA. And I don't think those same pins can be used for I/O planning since they are automatically constrained whenever there's a PS 7 IP (which is NOT present in this simulation scenario and is substituted by my own AXI transactors).

 

2. Should I be looking to simply removing my own resetn stimulus and only relying on the assign glbl.GSR = GSR type assignment to reset all my sequential elements in the design? If so I suspect I can't use this same setup for both functional as well as timing-sim, since in the functional sim, every FF in my design expects an asynchronous reset without really understanding that there's  GSR, isn't this so? 

 

3. Essentially it boils down to me not quite understanding how the testbench reset stimulus in general can be migrated from a functional simulation to a timing simulation.

 

 

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