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cjmaclean
Visitor
Visitor
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Registered: ‎12-14-2015

Are systemverilog program blocks supported in vivado 14.4 design suite

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Hi

 

Does vivado 14.4 design suite support program blocks? The following shows that Vivado is missing the required file test. Thanks

 

 

program test();

initial

begin

...

end

endprogram

 

module moduleTest();

 

test test1();

 

endmodule

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vijayak
Xilinx Employee
Xilinx Employee
6,806 Views
Registered: ‎10-24-2013

Hi @cjmaclean

 

The list of supported SV constcuts are given in Appendix D of http://www.xilinx.com/support/documentation/sw_manuals/xilinx2014_4/ug900-vivado-logic-simulation.pdf

 

Thanks,Vijay
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muzaffer
Teacher
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Registered: ‎03-31-2012
program doesn't seem to be in the list of supported simulation constructs so it's probably not supported.
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vijayak
Xilinx Employee
Xilinx Employee
6,807 Views
Registered: ‎10-24-2013

Hi @cjmaclean

 

The list of supported SV constcuts are given in Appendix D of http://www.xilinx.com/support/documentation/sw_manuals/xilinx2014_4/ug900-vivado-logic-simulation.pdf

 

Thanks,Vijay
--------------------------------------------------------------------------------------------
Please mark the post as an answer "Accept as solution" in case it helped resolve your query.
Give kudos in case a post in case it guided to the solution.

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