cancel
Showing results for 
Show  only  | Search instead for 
Did you mean: 
Highlighted
4,129 Views
Registered: ‎08-06-2015

Artix 7: Spike behind IBUF

We're using a ZTEX USB-FPGA 2.16 board, which has an Artix 7 XC7A200T.

 

We are struggling with spikes on an input we use as reset. To debug, we have the following setup:

     

          FPGA
        ____________
       |            |
--------->-------->-----
       | IBUF   OBUF|
       |____________|

 

Using a scope, we see a spike on the output (which explains all our functional problems), but we don't see a spike on the input we supply. So this spike comes from inside the FPGA, probably from the IBUF.

 

The spike is correlated with activity on other pins, so we immediately suspected something like ground-bounce issues. We have ensured that the FPGA is well grounded (by connecting all ground pins to a common ground reference).

 

We have tried moving the input pin to different IO banks. We have tried moving other pins. We can see no difference.

 

We tried holding the rest of the design in hard reset, so only the few signals in question are active, and the problem persists.

 

Any ideas for what can cause this?

0 Kudos
Reply
1 Reply
Highlighted
Scholar
Scholar
4,093 Views
Registered: ‎02-27-2008

s,

 

This occurs after DONE goes high?  Befor the device is configured, and while it is being configured, the pin should either be tristate, or have the week pullup enabled if thst is selected by the HSWAPEN pin.

 

On power-up, the IO pin is undefined until the supply voltages are detected to be OK.  Before that, the device holds IO pins in the tristate condition, but a low Vcco voltages, a pin ,might appear as a logic 0 due to the protection diode being forward biased.

 

Have you che checked the signal integrity of your layout?  Might this be cross talk noise from an adjacent signal?  What happens when you load it with 1K ohms?

Austin Lesea
Principal Engineer
Xilinx San Jose
0 Kudos
Reply