11-08-2016 01:29 AM
I've been experiencing the following problem:
I have a system with an AXI master accessing periodically several slaves in read and write mode. From time to time the read transactions just stop working. I observed the AXI interconnect signals with a ILA and I noticed that the read transactions are issued by the master ("left"side of the AXI interconnect) but are not propagated to the slaves ("right" side of the AXI interconnect).
I checked the addresses and they are correct (ie: they belong to specific slaves in the address map).
Is there some kind of (mis)behavior from a slave that could cause the AXI interconnect to hang in such a way?
Thanks for your help
11-30-2016 07:21 AM
11-30-2016 07:44 AM
11-30-2016 08:33 AM
Xilinx has some new synthesizable "verification" IP that you can instantiate on all your AXI busses to verify adherence to the AXI protocol. The IP is "axi_protocol_checker_v1_1". It's a passive probe - won't affect any operations, but will monitor the indicated bus. You can add that to every AXI bus in your design, (bring out the failure indicators to some monitor point - i.e your ILA).
The axi IC is very sensitive to protocol errors. I.e. invalid [rb]last can send the IC off into the weeds. The protocol checker may help you in diagnostics.
12-01-2016 12:11 AM
...Also make sure that the bandwidth usage of the interconnect is not too high if you have multiple masters connected to it. If you have a single master this shouldn't be a problem.
I actually have two masters: the first accessing periodically the bus with low bandwidth, the second that could eventually generate high traffic. What could it happen id the bandwidth usage of the interconnect is "too high"? Ans what do you mean by "too high"?
12-01-2016 12:25 AM
@krynn1978 a multi-master interconnect can have bandwidth issues if multiple masters try to talk to the same slave at a rate which cannot be sustained by the slave. Another possible issue is the total throughput of the interconnect might be too low if multiple masters are trying to talk to multiple slaves. This can be addressed by selecting a different optimization for the interconnect (ie maximize performance at a cost of increased area)
12-01-2016 12:40 AM
@muzaffer thanks for the explanation. What I still don't get is: what exactly happens when the maximum bandwidth for a certain system is exceeded? AXI supports backpressure, so if everything works, the masters should be just slowed down. Or not? Should I expect the ACI IC hanging because of excessive traffic?