05-11-2017 05:38 AM
I read the documentation of xilinx regarding BRAM and I don't understand for what reason should I use the output register. According the document:
Note that each optional register stage used adds an additional clock cycle of latency to the
05-11-2017 06:33 AM
From UG473 p20:
"The optional output registers improve design performance by eliminating routing delay to the CLB flip-flops for pipelined operation. An independent clock and clock enable input is provided for these output registers. As a result the output data registers hold the value independent of the input register operation."
05-11-2017 08:00 AM
You didn't mention which part you're using, but as an example Artix-7 in a -2 speed grade lists a maximum BRAM frequency of 460.83 MHz. This represents a period of 2.17 ns. The clock to output without the output register is listed at 2.13 ns for the same parts. That means you have only 40 ps of available time for routing delay and setup to a fabric flip-flop if you don't use the internal registers. With the internal registers, the clock to output is specified as 0.74 ns, which gives you much more time (1.43 ns) to meet setup to the next sequential element in the design.
If your design is running at much lower frequencies, then it's often preferable not to use the internal registers so you can reduce the address to data out delay by one clock cycle.
05-12-2017 05:10 AM
@sarit8 as you mention, using the output register adds a cycle of latency but not having it causes a long combinational path from the last driver in the ram to the first flop in the fabric. This reduces the realizable clock speed of the system. Memory read latency can usually be compensated for in the rest of the system so a higher clock frequency is preferable in most cases. If you fall into this case, it is suggested that you use the output register. If you can't tolerate the latency this will cause you will have a lower clock speed overall but one fewer cycles in the critical #of cycles to decision path.