Block RAM runtime data

[sachiniisc]

I have couple of questions?

1) Is there a tcl script to log the entire memory content of Block RAM to a text file during behavioral simulation in Vivado?

Eg:

a tcl script which takes BRAM instance and a filename as argument writes the content of BRAM to the provided filename (say in coe format)

2) Is there a tcl script to initialize the contents of Block RAM during simulation?

I know .coe file can initialize before start of simulation. But I want to know if there is a way to load during run time through tcl script.

Eg:

run 100ns

<braminstance>.load(file1.coe)

run 50ns

<braminstance>.load(file2.coe)

[thakurr]

Hi @sachiniisc

Please try the tcl commands mentioned in page 466, 999 of UG835:

https://www.xilinx.com/support/documentation/sw_manuals/xilinx2016_4/ug835-vivado-tcl-commands.pdf

Regards

Rohit

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[sachiniisc]

@thakurr

You mentioned get_ips and set_param utilities. However which parameter of Block RAM IP corresponds to memory contents. I am unable to see this from IP documentation.

[thakurr]

Hi @sachiniisc

Did you check the link i gave you in my last post? Page 466, 999 clearly mentions two commands:

generate_mem_files <directory>   This commands generates MEM files in the specified directory for use during simulation.

read_mem <files>     This command reads memory files of type MEM, DAT, or COE, and adds the files to the in-memory design, or the current project, to initialize BRAM memory for behavioral simulation, synthesis and post-synthesis simulation.

Please refer the below link :

https://www.xilinx.com/support/documentation/sw_manuals/xilinx2016_4/ug835-vivado-tcl-commands.pdf

Hope this helps.

Regards

Rohit

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[sachiniisc]

@thakurr

First of all sorry I was looking at an earlier version of tcl command reference hence the confusion.

read_mem<files> is just adding coe file to the project. What I want is it to be loaded into the memory of a particular block ram instance during simulation. After running simulation for a fixed number of clock cycles, I want another coe file to be loaded to replace the memory contents and continue with the simulation.

Anything I am missing here?

Please note that I am not using any embedded processor based design.