01-07-2015 07:35 AM
We have a design that we would like to fit in a CPLD or FPGA, we have extremely limited experience with both technologies, and need help to determine which technology and which part in the particular technology would be suitable. I have attached block diagrams to accompany the following description, the block diagram show two possible ways of implementing what we need.
What we need to implement in the CPLD or FPGA is:
16 counters of 18 bits each that can count at a rate of 1 MHz.
Logic to provide a serial bus to read the 16 counters.
The ability to read the previous counter results while new counting is occurring, (i.e. latches).
We need a very small package (footprint)
And as low power as is possible.
The attached pdf will give more insight to the requirement.
Your assistance is appreciated.
01-07-2015 10:37 AM
Contact Xilinx distributors from the below link and share your design details, so that they will guide you appropriately
01-07-2015 09:35 PM
spartan-3an fpga might meet your design requirment, you can check the logic resources in the datasheet and the select suitable fpga
coolrunner-II cpld details can be found in the link
you can download the webpack ISE tool for design and implementation. Hope you are comfortable with hdls(vhdl/verilog)