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sachiniisc
Observer
Observer
5,695 Views
Registered: ‎11-14-2016

Constraint file

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I am trying to use PCIe DMA to transfer data from PC to Kintex Ultrascale device.

 

I am following the steps in the link below for driver configuration:

https://www.xilinx.com/support/answers/65444.html

 

The IP is instantiated with the steps explained in the following video by Xilinx

https://www.youtube.com/watch?v=TzzzM97L4HI&t=2s

 

However my board is HTG-K800 (by HiTech Global). How to get the corresponding constraint (xdc) file.

Other than the constraint file, is there anything else I need to change to get the example to work?

1 Solution

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gnarahar
Moderator
Moderator
9,920 Views
Registered: ‎07-23-2015

@sachiniisc Kintex ultrascale is available in 2 Eval Boards, KCU105 and KCU1250. Constraints are available in the User Guides

 

KCU105: http://www.xilinx.com/support/documentation/boards_and_kits/kcu105/ug917-kcu105-eval-bd.pdf   Appx.D

 

KCU1250: http://www.xilinx.com/support/documentation/boards_and_kits/kcu1250/ug1057-kcu1250-char-bd.pdf  Appx.C

 

But please be aware that Constraint file depends on your board connectivity i.e. which pin of FPGA is connected to which interface. 

You can use the above for reference on constraint file format. 

 

 

- Giri
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7 Replies
balkris
Xilinx Employee
Xilinx Employee
5,691 Views
Registered: ‎08-01-2008
you need to check with board vendor. They must have provided master XDC file which contain all the details. In case not provided ask for board files which must have pin details. Refer the core product guide for constraint information

You can check constraints guide here
https://www.xilinx.com/support/documentation/sw_manuals/xilinx2016_2/ug903-vivado-using-constraints.pdf
Thanks and Regards
Balkrishan
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gnarahar
Moderator
Moderator
5,682 Views
Registered: ‎07-23-2015

@sachiniisc Since you have HiTech Global board bought from them, contact them for the User Manual & Schematics. The User Manual should list the XDC constraints. http://www.hitechglobal.com/boards/kintex-ultrascale.htm

 

They also have reference designs you could use to test the board. 

 

If you want to write your own constraints, you can refer to UG link provided in above post. However, it would be easier and quicker for you to get the Manual from HiTech global for quicker setup. 

 

htg-k800.JPG

- Giri
------------------------------------------------------------------------------------------------------------------------
Don’t forget to reply, kudo, and accept as solution.
If starting with Versal take a look at our Versal Design Process Hub and our Versal Blogs
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gnarahar
Moderator
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5,634 Views
Registered: ‎07-23-2015

@sachiniisc Were you able to get the required files?

- Giri
------------------------------------------------------------------------------------------------------------------------
Don’t forget to reply, kudo, and accept as solution.
If starting with Versal take a look at our Versal Design Process Hub and our Versal Blogs
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sachiniisc
Observer
Observer
5,627 Views
Registered: ‎11-14-2016

 

@gnaraharI got a sample constraint file. I am now working on it to bring up PCIe-DMA example design as shown in the video below:

https://www.youtube.com/watch?v=TzzzM97L4HI

 

Do you see any change to be done other than the constraint file change? Should there be any change in the driver?

 

The video explains the design from block design method. Is it ok if I do it by integrating individual IP in a separate top level file? Is there something to be taken care while doing so?

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sethus
Xilinx Employee
Xilinx Employee
5,619 Views
Registered: ‎11-25-2015

Hi @sachiniisc,

 

Follow the video which explains from scratch how to create an PCIe DMA design..

 

Make sure it works as expected and it's performance numbers are matching for you as mentioned

 

Please refer AR 68049 which we released recently with expected performance numbers

 

Once everything is up and running then go with your own customization which will make your debug easier

 

Thanks,

Sethu

sachiniisc
Observer
Observer
5,571 Views
Registered: ‎11-14-2016

@sethus @gnarahar @balkris

Can you provide the constraint file for Xilinx board so that I can do the corresponding changes for my board.

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gnarahar
Moderator
Moderator
9,921 Views
Registered: ‎07-23-2015

@sachiniisc Kintex ultrascale is available in 2 Eval Boards, KCU105 and KCU1250. Constraints are available in the User Guides

 

KCU105: http://www.xilinx.com/support/documentation/boards_and_kits/kcu105/ug917-kcu105-eval-bd.pdf   Appx.D

 

KCU1250: http://www.xilinx.com/support/documentation/boards_and_kits/kcu1250/ug1057-kcu1250-char-bd.pdf  Appx.C

 

But please be aware that Constraint file depends on your board connectivity i.e. which pin of FPGA is connected to which interface. 

You can use the above for reference on constraint file format. 

 

 

- Giri
------------------------------------------------------------------------------------------------------------------------
Don’t forget to reply, kudo, and accept as solution.
If starting with Versal take a look at our Versal Design Process Hub and our Versal Blogs
------------------------------------------------------------------------------------------------------------------------

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