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Visitor
Visitor
5,145 Views
Registered: ‎05-23-2012

Counter with DATA inputs?

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Hey, I am stucked with an assingment at my school, well not really stucked, but my working solution does not follow the instruction given. 

 

In the instruction, it says that the counter should have all inputs and outputs the 74190-counter have. Which means these inputs: Data_in (A, B, C and D), Clock, Load, Enable. And the outputs: Q and ripple clock.

I get everything to work accept ripple clock (cus I don't really know what that is ^^ )

 

Anyhow, the ripple clock is not the central thing I am concerned about, it is that I have no DATA_in as an input. I used two integer values with the range 0-15 (present_state, next_state) which I later on passed on the output. It all works well, BUT I do not use the DATA_IN as an input in the instructions.

 

So I started googling on the net. This site: http://www.cs.uregina.ca/Links/class-info/301/counter/lecture.html, was one of the first I found and even the next comming 20 pages or so hade one thing in common. And not supringsly neither one of those sites used any input values like DATA_IN while creating the enitity.

 

Therefore my question is:

 

1) How do I add and input like DATA_IN to an Entitiy? If it is possible.

 

2) Why has no one else done that?

 

3) If you know what ripple_clock might be, you could be nice and explain it. It would save me some time. But I didnot creat this thread because of that. Its only bonus. I want to solve 1 & 2-questions primary.

 

I'm sorry if my english is kind a messy. I don't write in english that often. I read a lot better than I write, so don't worry about writing the answers in too complex english.

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Professor
Professor
6,524 Views
Registered: ‎08-14-2007

Re: Counter with DATA inputs?

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You can add an port to your entity just the way you input the clock and reset.

 

for example:

 

          DATA_IN      : in std_logic_vector(3 downto 0);

Then you need logic to set the output bits to the value of DATA_IN.  The "A" "B" "C" "D" inputs

of the old TTL circuit would correspont to bits DATA_IN(0), DATA_IN(1), DATA_IN(2), DATA_IN(3).

 

In an FPGA, counters don't typically have asynchronous load inputs.  If you look at the

structure of a logic cell, the flip-flop would need to have both asynchronous set and reset

inputs.  Some older Xilinx parts have this feature, but newer parts do not.

 

Ripple clocking means that a counter is made of individual toggle flip-flops

with each flip-flop's output connected to the next flip-flop's clock input.  A ripple

counter was a simpler way to make counters when additional logic was expensive,

as when the 7400 series was in use.  It is a very bad idea to make counters this

way in an FPGA.  FPGA design works best when all signals are synchronous to

a single clock.

 

Perhaps if you post a link to a 74190 data sheet, I might give you more pointers.

I recently cleaned my office and threw away the old TTL data books.

 

- Gabor

-- Gabor

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Teacher
Teacher
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Registered: ‎09-09-2010

Re: Counter with DATA inputs?

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Impossible to comment on code not seen...

------------------------------------------
"If it don't work in simulation, it won't work on the board."
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Highlighted
Professor
Professor
6,525 Views
Registered: ‎08-14-2007

Re: Counter with DATA inputs?

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You can add an port to your entity just the way you input the clock and reset.

 

for example:

 

          DATA_IN      : in std_logic_vector(3 downto 0);

Then you need logic to set the output bits to the value of DATA_IN.  The "A" "B" "C" "D" inputs

of the old TTL circuit would correspont to bits DATA_IN(0), DATA_IN(1), DATA_IN(2), DATA_IN(3).

 

In an FPGA, counters don't typically have asynchronous load inputs.  If you look at the

structure of a logic cell, the flip-flop would need to have both asynchronous set and reset

inputs.  Some older Xilinx parts have this feature, but newer parts do not.

 

Ripple clocking means that a counter is made of individual toggle flip-flops

with each flip-flop's output connected to the next flip-flop's clock input.  A ripple

counter was a simpler way to make counters when additional logic was expensive,

as when the 7400 series was in use.  It is a very bad idea to make counters this

way in an FPGA.  FPGA design works best when all signals are synchronous to

a single clock.

 

Perhaps if you post a link to a 74190 data sheet, I might give you more pointers.

I recently cleaned my office and threw away the old TTL data books.

 

- Gabor

-- Gabor

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Voyager
Voyager
5,136 Views
Registered: ‎04-02-2011

Re: Counter with DATA inputs?

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In the instruction, it says that the counter should have all inputs and outputs the 74190-counter have. Which means these inputs: Data_in (A, B, C and D), Clock, Load, Enable. And the outputs: Q and ripple clock.

I get everything to work accept ripple clock (cus I don't really know what that is ^^ )


Motorola's 74190 is a synchronous UP/DOWN BCD Decade (8421) Counter.

Specifically 74910 should have

 

CE--> Count Enable (Active LOW) Input.

 

CP--> Clock Pulse (Active HIGH going edge) Input

 

U/D--> Up/Down Count Control Input.

 


 

PL--> Parallel Load Control (Active LOW) Input.

 

Pn--> Parallel Data Inputs.

 

Qn--> Flip-Flop Outputs.

 

RC--> Ripple Clock Output.

 

TC--> Terminal Count Output.

The RC output is normally HIGH. When CE is LOW and TC is HIGH, the RC output will go LOW when the
clock next goes LOW and will stay LOW until the clock goes HIGH again. This feature simplifies the design of multi-stage counters.

 


Therefore my question is:

 

1) How do I add and input like DATA_IN to an Entitiy? If it is possible.

 

2) Why has no one else done that?

 

 


 

You should have very good knowledge of Digital Design.

If,you should start learning verilog/vhdl and translate Digital circuits into that.

 

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Visitor
Visitor
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Registered: ‎05-23-2012

Re: Counter with DATA inputs?

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Thanks man, really made things clear

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Visitor
Visitor
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Registered: ‎05-23-2012

Re: Counter with DATA inputs?

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And if I have more problems I will provide the datasheets for you.
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Professor
Professor
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Registered: ‎08-14-2007

Re: Counter with DATA inputs?

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The RC output is normally HIGH. When CE is LOW and TC is HIGH, the RC output will go LOW when the
clock next goes LOW and will stay LOW until the clock goes HIGH again. This feature simplifies the design of multi-stage counters.

 

In the FPGA world, this is known as a "gated clock" and considered bad practice.  However

in the days of the 7400 series, it probably did save some logic.  It also guaranteed a large

delay between the outputs of the first 74190 and the outputs of the 74190 clocked by its

RC output.

 

Implementing a gated clock as an output of a modern FPGA is not easy.  I think you'll find

that at least for Spartan 6 parts, you can't do this with a simple gate because there is no

link betwen the global clock route and the normal fabric routing to bring the clock signal

to a LUT input.

 

Of course if you only need to write code for simulation, you can do whatever you want.

Sometimes the choice of projects for courses like yours doesn't make a lot of sense.

 

- Gabor

-- Gabor
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