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pavansed23
Visitor
Visitor
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Registered: ‎03-10-2016

[DRC 23-20] Rule violation (INBB-3) Black Box Instances

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Hi,

 

I'm working on a project where i'm packaging an EDIF netlist into an IP block and using it to build a block design.

 

When I make the connections in the bd and synthesize it, synth passes.But I am encountering the following error during opt_design.

 

[DRC 23-20] Rule violation (INBB-3) Black Box Instances - Cell 'design_1_i/core_0/inst/ac/ALEG_i' of type 'design_1_i/core_0/inst/shr/A_i/RTL_MUX1091' has undefined contents and is considered a black box. The contents of this cell must be defined for opt_design to complete successfully.

 

core_0 is the IP generated out of netlists.

 

The project built with the HDL instead of netlist works well, and passes through opt_design. i.e. I create an IP block using HDL source files instead of Netlist(EDIF) and build a bd, and everything goes smoothly and bitfile is generated.

 

I have cheked out the solutions provided in the following threads, but it has not helped.

 

https://forums.xilinx.com/t5/Implementation/INBB-3-The-contents-of-this-cell-must-be-deifned-for-opt-design/td-p/672542

 

I tried both the project and non-project modes and still no luck.

 

Has anyone got a solution for this?

 

I am using Vivado 2015.4 and I want to build my project for kc705. Any Help here would be appreciated.

 

Thanks,

Pavan

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pavansed23
Visitor
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Registered: ‎03-10-2016

Ok, from what I can gather, the error was due to the edif being written post RTL elaboration. So, I tried the two things below.

 

1. Writing out edif after synthesis.

2. Writing out edif after implementation.

 

Oddly, the 2nd option worked and not the first.

 

I had hoped both would work. There is no clear documentation about this as edif can be written out after elaboration,synthesis as well as implementation. Well, thanks for the responses @vuppala @siktap  ,your inputs led me to revisit and solve this.

 

Thanks in particular to @vemulad.

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vuppala
Xilinx Employee
Xilinx Employee
15,335 Views
Registered: ‎04-16-2012

Hi @pavansed23

 

When you generate the output products of custom IP, is the edif netlist generated??

If not, you have to package the custom IP by adding the edif netlist to the output products.

 

Thanks,

Vinay

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siktap
Scholar
Scholar
15,323 Views
Registered: ‎06-14-2012

Hi Pavan

Please see if this helps.

http://www.xilinx.com/support/answers/54074.html

 

Regards

Sikta

vemulad
Xilinx Employee
Xilinx Employee
15,318 Views
Registered: ‎09-20-2012

Hi @pavansed23

 

How are you generating the EDIF file?

Thanks,
Deepika.
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stv0g
Observer
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Registered: ‎02-26-2016

I have a similar problem.

 

In our case, the netlist is provided by one of our partners.

They only provide us with a syntesized netlist because of copyright reasons.

 

Am I right in assuming that adding a stub HDL declaration for synthesis should solve this error?

In this case I will try to use the 

netgen

command to get a HDL entity declaration. Thanks

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pavansed23
Visitor
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Registered: ‎03-10-2016

@vuppala Yes, the EDIF netlist is being generated along with the instantiation stub. I am not explicitly adding the .xci, I just add IP from the IP catalog, by specifying my own repository(where my IP definition exists) and regenerate the IP (by that I mean the output products, which are the dcp and instantiation template) and synthesize it. This runs just fine.

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pavansed23
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Registered: ‎03-10-2016

@vemulad I am creating a top level wrapper and adding all my source files into it ins a separate project. I use the write_edif command to get the netlist file.

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pavansed23
Visitor
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Registered: ‎03-10-2016

Ok, from what I can gather, the error was due to the edif being written post RTL elaboration. So, I tried the two things below.

 

1. Writing out edif after synthesis.

2. Writing out edif after implementation.

 

Oddly, the 2nd option worked and not the first.

 

I had hoped both would work. There is no clear documentation about this as edif can be written out after elaboration,synthesis as well as implementation. Well, thanks for the responses @vuppala @siktap  ,your inputs led me to revisit and solve this.

 

Thanks in particular to @vemulad.

View solution in original post

Anonymous
Not applicable
9,861 Views

Hello,

 

I'm using VIVADO HLS 2015.4 and VIVADO 2015.4 . 

 

My C++ Top level function basically should reproduce a sinewave using the function "sin" (the code is attached to this message)

 

 

 

After the Synthesis, I run the implementation and I get this error (you can see the picture here below).

 

 

sinError.JPG

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Anonymous
Not applicable
9,859 Views

 

Anyone has an idea on how to remove this error?

Thank you

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dam.balzani
Newbie
Newbie
3,206 Views
Registered: ‎02-25-2017

hi everybody,

i'm student and i got this error during implementation process

 

[DRC 23-20] Rule violation (INBB-3) Black Box Instances - Cell 'rtve_3_1_oz745_4x_top_i/cpu_world/axi_interconnect_1/s00_mmu' of type 'rtve_3_1_oz745_4x_top_i/cpu_world/axi_interconnect_1/s00_mmu/rtve_3_1_oz745_4x_top_s00_mmu_0' has undefined contents and is considered a black box. The contents of this cell must be defined for opt_design to complete successfully.

 

Can you help me?

Thanks

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