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vaddi_iitg
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Registered: ‎07-30-2014

Differential clock to single ended Clock

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Hi all I am using a zynq zc702 board. I have a differential clock comming from the board. now i want to make it into a single clock. Now i know that there are several buffers like IOBUF, IBUFGDS,IBUFDS etc... What are the difference between these. And which should i use.

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anusheel
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Registered: ‎07-21-2014

Hi,

 

Clock constraints do not results in IOSTD errors.

As this issue is already active on other thread, close this thread by marking the solution.

 

Thanks,
Anusheel
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vuppala
Xilinx Employee
Xilinx Employee
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Registered: ‎04-16-2012

Hello,

 

you can use IBUFGDS for the clock to convert from differential clock to single.

See more description in the following user guide: http://www.xilinx.com/support/documentation/sw_manuals/xilinx14_7/7series_hdl.pdf (page no. 177)

 

Thanks,

Vinay

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pulim
Xilinx Employee
Xilinx Employee
19,669 Views
Registered: ‎02-16-2014

Hi,

 

yes, you should be using IBUFGDS.

This design element is a dedicated differential signaling input buffer for connection to the clock buffer (BUFG) or

MMCM.

 

IOBUF is a bidirectional single-ended I/O Buffer used to connect internal logic to an external bidirectional pin.

 

IBUFDS is differential signalling input buffer that is used differential inputs.

 

 

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vaddi_iitg
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19,645 Views
Registered: ‎07-30-2014

But i have a problem. IBUFGDS template is not there in Vivado. And if i am using IBUFDS i am getting this error while generating bitstream

 

  • [Drc 23-20] Rule violation (IOSTDTYPE-1) IOStandard Type - I/O port systemClockN is Single-Ended but has an IOStandard of LVDS_25 which can only support Differential
    • [Drc 23-20] Rule violation (IOSTDTYPE-1) IOStandard Type - I/O port systemClockP is Single-Ended but has an IOStandard of LVDS_25 which can only support Differential
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anusheel
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19,635 Views
Registered: ‎07-21-2014

Hi,

 

This error may occur if I/O port is single ended and LVDS_25 is used thats what error message says.

 

Make sure you are using right constraints. Which device are you targeting? Show your constraints here.

 

Thanks,
Anusheel
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vaddi_iitg
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Registered: ‎07-30-2014

I am using ZC702 board. I am using System Clock. In use Guide pg 28. D18 and C19 for P and N. But i did not give clock constraints is that the problem??

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anusheel
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28,021 Views
Registered: ‎07-21-2014

Hi,

 

Clock constraints do not results in IOSTD errors.

As this issue is already active on other thread, close this thread by marking the solution.

 

Thanks,
Anusheel
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vemulad
Xilinx Employee
Xilinx Employee
19,609 Views
Registered: ‎09-20-2012

Hi,

 

Open synthesized design and check if the IBUFDS inputs and output are connected properly or not.

 

Thanks,

Deepika.

Thanks,
Deepika.
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