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Visitor
Posts: 12
Registered: ‎05-09-2017
Accepted Solution

Does Vivado + SoC support only AXI IP Cores?

Hi all!

 

Does Vivado + Zynq support only AXI IP Cores??

 

I have some projects on 6 Series FPGAs + ISE and decided to make the step to SoC-Zynq and implicit Vivado. I just noticed that I can use only AXI IP Cores (Math, Transform, Filters, etc, etc). Is this right?? Or am I missing something?

 

I have a ton of already written modules for FPGA which I though that I can easily re-use in PL from SoC after I generate only the new IP Cores in Vivado. But I found only AXI ??

 

If everything is with AXI: Could someone give me a link to a good tutorial for sending data from PL to FIR (or something else) using AXI. Thank you.

 

Regards,

Paul


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Highlighted
Teacher
Posts: 5,041
Registered: ‎03-31-2012

Re: Does Vivado + SoC support only AXI IP Cores?

@paul.tutzu axi proper might be a little complicated but axi-streams are quite easy. Effectively they implement the same interface you mention below, the only addition is the extra handshake which indicates the slave is ready ie master says it has valid data (tvalid) and the slave says it's ready to receive it (tready), when  both are active tdata is consumed by the slave and the process is repeated (ie the master can keep the valid high and present new data etc.)

 

As to FIR with axi-streams with data coming from PL, you just need to implement an axi stream master, say something which gets data from ADC and provides it to the FIR block. This is, as above, quite simple.

 

If you need to read data from DDR you need an axi master proper which is somewhat more complicated. Getting data from PS is easier as you can create an axi-lite slave interface which receives one word at a time from PS but you have to add an axi-stream master to it.

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Xilinx Employee
Posts: 1,185
Registered: ‎11-09-2015

Re: Does Vivado + SoC support only AXI IP Cores?

HI @paul.tutzu,

 

You can put any type of IP in the Programmable Logic of a Zynq. AXI IP is only to control the IP (some IPs does not require to be configured (i.e. registers set by the SW))

 

Hope that helps,

 

Regards,

 

Florent

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Visitor
Posts: 12
Registered: ‎05-09-2017

Re: Does Vivado + SoC support only AXI IP Cores?

Hello @florentw,

 

thank you for your reply. First of all I have absolutely no experience with AXI so please be patient with me :) 

 

1. I'm searching in Vivado for the equivalent of: ISE \\ Core Generator \\ FIR Compiler without AXI4 - Stream. I look for a vhdl wrapper where I have direct access to ports like: clk, rfd, rdy, din, dout. The good old *.vhd generated by CoreGenerator with XilinxCoreLib.fir_compiler_v5_0. 

But I still have to regenerate somehow the cores. In the wrapper are signals like: c_family => "spartan6", cxdevice_family => "spartan6", and so on. I have to regenerate it for Zynq.

 

2. I will also want to give it a try with FIR Compiler with AXI4 - Stream, do add it in the Block Design and then to connect it to Processor or PL. Are there some tutorials how to do it? I read the AXI Reference Guide, AXI Interconnect Logic IP,etc, etc but I don't know how to put them together and how to access from PL the data.

 

Thank you!

Paul

Xilinx Employee
Posts: 1,185
Registered: ‎11-09-2015

Re: Does Vivado + SoC support only AXI IP Cores?

Hi @paul.tutzu,

 

You may want to look at the tutorial from Adam Taylor (link) for using the zynq ;-)

 

There is also the UG940, UG995 and the UG1165

 

Regards,

 

Florent

--------------------------------------------------------------------------------------------
Please mark an answer "Accept as solution" if a post has the solution to your issue.
--------------------------------------------------------------------------------------------
Highlighted
Teacher
Posts: 5,041
Registered: ‎03-31-2012

Re: Does Vivado + SoC support only AXI IP Cores?

@paul.tutzu axi proper might be a little complicated but axi-streams are quite easy. Effectively they implement the same interface you mention below, the only addition is the extra handshake which indicates the slave is ready ie master says it has valid data (tvalid) and the slave says it's ready to receive it (tready), when  both are active tdata is consumed by the slave and the process is repeated (ie the master can keep the valid high and present new data etc.)

 

As to FIR with axi-streams with data coming from PL, you just need to implement an axi stream master, say something which gets data from ADC and provides it to the FIR block. This is, as above, quite simple.

 

If you need to read data from DDR you need an axi master proper which is somewhat more complicated. Getting data from PS is easier as you can create an axi-lite slave interface which receives one word at a time from PS but you have to add an axi-stream master to it.

- Please mark the Answer as "Accept as solution" if information provided is helpful.
Give Kudos to a post which you think is helpful and reply oriented.