07-02-2017 02:32 AM
Is there any information a bout the ESD requirement concerning Zinq Ultarscale+, I have found at UG116 some reference about older families but not Zinq Ultrascale+ .....
07-02-2017 02:57 AM - edited 07-02-2017 02:58 AM
There is a link on PCB design doc. https://www.xilinx.com/support/documentation/user_guides/ug583-ultrascale-pcb-design.pdf (chapter 10) pointing to JEDEC ESD guidelines https://www.jedec.org/standards-documents/docs/jep-155
07-05-2017 12:59 AM - edited 07-05-2017 02:09 AM
MIL-STD-883 method 3015 is used for ESD testing.The specification is available for download at: http://www.dscc.dla.mil/
The ESD & other reliability test reports for all devices ( Zinq Ultrascale+ device) can be found in https://www.xilinx.com/support/documentation/user_guides/ug116.pdf
The most recent ESD information is available in the Quarterly Report. it is located in the Quality and Reliability area of the Xilinx Web site at: https://www.xilinx.com/support/quality.html
-A good first port of call is (Xilinx Answer 3982)
-Xilinx recommends not to leave any pins (including unused pins) floating. Leaving pins floating reduces their ESD protection. For more information, see (Xilinx Answer 11906). (Xilinx Answer 9048) lists the pins that have clamp diodes.
-(Xilinx Answer 3982) contains links to the Reliability Report which contains the results of Xilinx testing for ESD.
-The following white paper https://www.xilinx.com/support/documentation/white_papers/wp433-Mitigating-ESD-EOS.pdf written for 7-series FPGA's But some general information (Which was not device specific) applicable for Zynq Ultrascale+ devices also