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gajanan
Newbie
Newbie
2,765 Views
Registered: ‎11-28-2016

FATAL_ERROR:Xst:Portability/export/Port_Main.h:143:1.17 in NI FPGA code

Dear Team,

 

While compiling NI FPGA based code, we are getting below error.

 

### Generate Xilinx IP (Generate Xilinx IP) ###

### Synthesize - XST (Synthesize - XST) ###
toplevel_gen
Reading design: toplevel_gen.prj

=========================================================================
* HDL Compilation *
=========================================================================
Compiling vhdl file "D:/NIFPGA/jobs/Rw6D31z_B3Vr00M/PkgNiUtilities.vhd" in Library work.
Package <PkgNiUtilities> compiled.
Package body <PkgNiUtilities> compiled.
Compiling vhdl file "D:/NIFPGA/jobs/Rw6D31z_B3Vr00M/PkgNiFpgaUtilities.vhd" in Library work.
Package <PkgNiFpgaUtilities> compiled.
Package body <PkgNiFpgaUtilities> compiled.
Compiling vhdl file "D:/NIFPGA/jobs/Rw6D31z_B3Vr00M/DFlop.vhd" in Library work.
Entity <DFlop> compiled.
Entity <DFlop> (Architecture <rtl>) compiled.
Compiling vhdl file "D:/NIFPGA/jobs/Rw6D31z_B3Vr00M/PkgFxp.vhd" in Library work.
Package <PkgFxp> compiled.
Package body <PkgFxp> compiled.
Compiling vhdl file "D:/NIFPGA/jobs/Rw6D31z_B3Vr00M/DFlopSLV.vhd" in Library work.
Entity <DFlopSLV> compiled.
Entity <DFlopSLV> (Architecture <rtl>) compiled.
Compiling vhdl file "D:/NIFPGA/jobs/Rw6D31z_B3Vr00M/PkgGray.vhd" in Library work.
Package <PkgGray> compiled.
Package body <PkgGray> compiled.
Compiling vhdl file "D:/NIFPGA/jobs/Rw6D31z_B3Vr00M/PkgFxpArithmetic.vhd" in Library work.
Package <PkgFxpArithmetic> compiled.
Package body <PkgFxpArithmetic> compiled.
Compiling vhdl file "D:/NIFPGA/jobs/Rw6D31z_B3Vr00M/DFlopBoolVec.vhd" in Library work.
Entity <DFlopBoolVec> compiled.
Entity <DFlopBoolVec> (Architecture <rtl>) compiled.
Compiling vhdl file "D:/NIFPGA/jobs/Rw6D31z_B3Vr00M/DFlopUnsigned.vhd" in Library work.
Entity <DFlopUnsigned> compiled.
Entity <DFlopUnsigned> (Architecture <rtl>) compiled.
Compiling vhdl file "D:/NIFPGA/jobs/Rw6D31z_B3Vr00M/DFlopGray.vhd" in Library work.
Entity <DFlopGray> compiled.
Entity <DFlopGray> (Architecture <rtl>) compiled.
Compiling vhdl file "D:/NIFPGA/jobs/Rw6D31z_B3Vr00M/FxpShiftCore.vhd" in Library work.
Entity <FxpShiftCore> compiled.
Entity <FxpShiftCore> (Architecture <rtl>) compiled.
Compiling vhdl file "D:/NIFPGA/jobs/Rw6D31z_B3Vr00M/NiFpgaDualPortRam_Inferred.vhd" in Library work.
Entity <NiFpgaDualPortRAM_Inferred> compiled.
Entity <NiFpgaDualPortRAM_Inferred> (Architecture <rtl>) compiled.
Compiling vhdl file "D:/NIFPGA/jobs/Rw6D31z_B3Vr00M/SyncFifoFlags.vhd" in Library work.
Entity <SyncFifoFlags> compiled.
Entity <SyncFifoFlags> (Architecture <rtl>) compiled.
Compiling vhdl file "D:/NIFPGA/jobs/Rw6D31z_B3Vr00M/GenDataValid.vhd" in Library work.
Entity <GenDataValid> compiled.
Entity <GenDataValid> (Architecture <rtl>) compiled.
Compiling vhdl file "D:/NIFPGA/jobs/Rw6D31z_B3Vr00M/PkgCommIntConfiguration.vhd" in Library work.
Package <PkgCommIntConfiguration> compiled.
Package body <PkgCommIntConfiguration> compiled.
Compiling vhdl file "D:/NIFPGA/jobs/Rw6D31z_B3Vr00M/DFlopSlvResetVal.vhd" in Library work.
Entity <DFlopSlvResetVal> compiled.
Entity <DFlopSlvResetVal> (Architecture <rtl>) compiled.
Compiling vhdl file "D:/NIFPGA/jobs/Rw6D31z_B3Vr00M/PulseSyncBase.vhd" in Library work.
Entity <PulseSyncBase> compiled.
Entity <PulseSyncBase> (Architecture <behavior>) compiled.
Compiling vhdl file "D:/NIFPGA/jobs/Rw6D31z_B3Vr00M/DoubleSyncAsyncInBase.vhd" in Library work.
Entity <DoubleSyncAsyncInBase> compiled.
Entity <DoubleSyncAsyncInBase> (Architecture <rtl>) compiled.
Compiling vhdl file "D:/NIFPGA/jobs/Rw6D31z_B3Vr00M/NiLvFxpEnableHandlerSlv.vhd" in Library work.
Entity <NiLvFxpEnableHandlerSlv> compiled.
Entity <NiLvFxpEnableHandlerSlv> (Architecture <rtl>) compiled.
Compiling vhdl file "D:/NIFPGA/jobs/Rw6D31z_B3Vr00M/PkgFloat.vhd" in Library work.
Package <PkgFloat> compiled.
Package body <PkgFloat> compiled.
Compiling vhdl file "D:/NIFPGA/jobs/Rw6D31z_B3Vr00M/FxpDynamicShift.vhd" in Library work.
Entity <FxpDynamicShift> compiled.
Entity <FxpDynamicShift> (Architecture <rtl>) compiled.
Compiling vhdl file "D:/NIFPGA/jobs/Rw6D31z_B3Vr00M/DFlopFallingEdge.vhd" in Library work.
Entity <DFlopFallingEdge> compiled.
Entity <DFlopFallingEdge> (Architecture <rtl>) compiled.
Compiling vhdl file "D:/NIFPGA/jobs/Rw6D31z_B3Vr00M/PkgNiFpgaFifoGenericValue.vhd" in Library work.
Package <PkgNiFpgaFifoGenericValue> compiled.
Compiling vhdl file "D:/NIFPGA/jobs/Rw6D31z_B3Vr00M/PkgNiFpgaCoresFifo.vhd" in Library work.
Package <PkgNiFpgaCoresFifo> compiled.
WARNING:HDLParsers:3534 - "D:/NIFPGA/jobs/Rw6D31z_B3Vr00M/PkgNiFpgaCoresFifo.vhd" Line 52. In the function ReturnMiteDmaReadMode, not all control paths contain a return statement.
Package body <PkgNiFpgaCoresFifo> compiled.
Compiling vhdl file "D:/NIFPGA/jobs/Rw6D31z_B3Vr00M/NiFpgaFifoFlags.vhd" in Library work.
Entity <NiFpgaFifoFlags> compiled.
Entity <NiFpgaFifoFlags> (Architecture <rtl>) compiled.
Compiling vhdl file "D:/NIFPGA/jobs/Rw6D31z_B3Vr00M/NiFpgaDualPortRam.vhd" in Library work.
Entity <NiFpgaDualPortRAM> compiled.
Entity <NiFpgaDualPortRAM> (Architecture <rtl>) compiled.
Compiling vhdl file "D:/NIFPGA/jobs/Rw6D31z_B3Vr00M/PkgCommunicationInterface.vhd" in Library work.
Package <PkgCommunicationInterface> compiled.
Package body <PkgCommunicationInterface> compiled.
Compiling vhdl file "D:/NIFPGA/jobs/Rw6D31z_B3Vr00M/HandshakeBase.vhd" in Library work.
Entity <HandshakeBase> compiled.
Entity <HandshakeBase> (Architecture <behavior>) compiled.
Compiling vhdl file "D:/NIFPGA/jobs/Rw6D31z_B3Vr00M/NiFpgaPulseSyncBaseWrapper.vhd" in Library work.
Entity <NiFpgaPulseSyncBaseWrapper> compiled.
Entity <NiFpgaPulseSyncBaseWrapper> (Architecture <rtl>) compiled.
Compiling vhdl file "D:/NIFPGA/jobs/Rw6D31z_B3Vr00M/PulseSyncBool.vhd" in Library work.
Entity <PulseSyncBool> compiled.
Entity <PulseSyncBool> (Architecture <behavior>) compiled.
Compiling vhdl file "D:/NIFPGA/jobs/Rw6D31z_B3Vr00M/DoubleSyncBase.vhd" in Library work.
Entity <DoubleSyncBase> compiled.
Entity <DoubleSyncBase> (Architecture <behavior>) compiled.
Compiling vhdl file "D:/NIFPGA/jobs/Rw6D31z_B3Vr00M/NiLvFxpEnableHandler.vhd" in Library work.
Entity <NiLvFxpEnableHandler> compiled.
Entity <NiLvFxpEnableHandler> (Architecture <rtl>) compiled.
Compiling vhdl file "D:/NIFPGA/jobs/Rw6D31z_B3Vr00M/NiLvFloatToFixedCore.vhd" in Library work.
Entity <NiLvFloatToFixedCore> compiled.
Entity <NiLvFloatToFixedCore> (Architecture <rtl>) compiled.
Compiling vhdl file "D:/NIFPGA/jobs/Rw6D31z_B3Vr00M/FxpNormalize.vhd" in Library work.
Entity <FxpNormalize> compiled.
Entity <FxpNormalize> (Architecture <rtl>) compiled.
Compiling vhdl file "D:/NIFPGA/jobs/Rw6D31z_B3Vr00M/DFlopBool.vhd" in Library work.
Entity <DFlopBool> compiled.
Entity <DFlopBool> (Architecture <rtl>) compiled.
Compiling vhdl file "D:/NIFPGA/jobs/Rw6D31z_B3Vr00M/DFlopBoolFallingEdge.vhd" in Library work.
Entity <DFlopBoolFallingEdge> compiled.
Entity <DFlopBoolFallingEdge> (Architecture <rtl>) compiled.
Compiling vhdl file "D:/NIFPGA/jobs/Rw6D31z_B3Vr00M/PkgNiFpgaFifo.vhd" in Library work.
Package <PkgNiFpgaFifo> compiled.
Package body <PkgNiFpgaFifo> compiled.
Compiling vhdl file "D:/NIFPGA/jobs/Rw6D31z_B3Vr00M/NiFpgaFlipFlopFifo.vhd" in Library work.
Entity <NiFpgaFlipFlopFifo> compiled.
Entity <NiFpgaFlipFlopFifo> (Architecture <rtl>) compiled.
Compiling vhdl file "D:/NIFPGA/jobs/Rw6D31z_B3Vr00M/FifoWriteAdapter.vhd" in Library work.
Entity <FifoWriteAdapter> compiled.
Entity <FifoWriteAdapter> (Architecture <rtl>) compiled.
Compiling vhdl file "D:/NIFPGA/jobs/Rw6D31z_B3Vr00M/NiFpgaFifo.vhd" in Library work.
Entity <NiFpgaFifo> compiled.
Entity <NiFpgaFifo> (Architecture <rtl>) compiled.
Compiling vhdl file "D:/NIFPGA/jobs/Rw6D31z_B3Vr00M/CpuDataWr.vhd" in Library work.
Entity <CpuDataWr> compiled.
Entity <CpuDataWr> (Architecture <rtl>) compiled.
Compiling vhdl file "D:/NIFPGA/jobs/Rw6D31z_B3Vr00M/DmaDisabler.vhd" in Library work.
Entity <DmaDisabler> compiled.
Entity <DmaDisabler> (Architecture <rtl>) compiled.
Compiling vhdl file "D:/NIFPGA/jobs/Rw6D31z_B3Vr00M/DmaMiteWriteRegs.vhd" in Library work.
Entity <DmaMiteWriteRegs> compiled.
Entity <DmaMiteWriteRegs> (Architecture <RTL>) compiled.
Compiling vhdl file "D:/NIFPGA/jobs/Rw6D31z_B3Vr00M/FifoReadAdapter.vhd" in Library work.
Entity <FifoReadAdapter> compiled.
Entity <FifoReadAdapter> (Architecture <rtl>) compiled.
Compiling vhdl file "D:/NIFPGA/jobs/Rw6D31z_B3Vr00M/HandshakeBool.vhd" in Library work.
Entity <HandshakeBool> compiled.
Entity <HandshakeBool> (Architecture <struct>) compiled.
Compiling vhdl file "D:/NIFPGA/jobs/Rw6D31z_B3Vr00M/CpuDataRd.vhd" in Library work.
Entity <CpuDataRd> compiled.
Entity <CpuDataRd> (Architecture <rtl>) compiled.
Compiling vhdl file "D:/NIFPGA/jobs/Rw6D31z_B3Vr00M/DmaMiteReadRegs.vhd" in Library work.
Entity <DmaMiteReadRegs> compiled.
Entity <DmaMiteReadRegs> (Architecture <RTL>) compiled.
Compiling vhdl file "D:/NIFPGA/jobs/Rw6D31z_B3Vr00M/DoubleSyncBool.vhd" in Library work.
Entity <DoubleSyncBool> compiled.
Entity <DoubleSyncBool> (Architecture <behavior>) compiled.
Compiling vhdl file "D:/NIFPGA/jobs/Rw6D31z_B3Vr00M/NiFpgaFifoPortReset.vhd" in Library work.
Entity <NiFpgaFifoPortReset> compiled.
Entity <NiFpgaFifoPortReset> (Architecture <rtl>) compiled.
Compiling vhdl file "D:/NIFPGA/jobs/Rw6D31z_B3Vr00M/PkgNiLvPrims.vhd" in Library work.
Package <PkgNiLvPrims> compiled.
Package body <PkgNiLvPrims> compiled.
Compiling vhdl file "D:/NIFPGA/jobs/Rw6D31z_B3Vr00M/NiLvFloatToFixed.vhd" in Library work.
Entity <NiLvFloatToFixed> compiled.
Entity <NiLvFloatToFixed> (Architecture <rtl>) compiled.
Compiling vhdl file "D:/NIFPGA/jobs/Rw6D31z_B3Vr00M/NiLvFxpCoerce.vhd" in Library work.
Entity <NiLvFxpCoerce> compiled.
Entity <NiLvFxpCoerce> (Architecture <rtl>) compiled.
Compiling vhdl file "D:/NIFPGA/jobs/Rw6D31z_B3Vr00M/NiLvFixedToFloat.vhd" in Library work.
Entity <NiLvFixedToFloat> compiled.
Entity <NiLvFixedToFloat> (Architecture <rtl>) compiled.
Compiling vhdl file "D:/NIFPGA/jobs/Rw6D31z_B3Vr00M/ResetSync.vhd" in Library work.
Entity <ResetSync> compiled.
Entity <ResetSync> (Architecture <rtl>) compiled.
Compiling vhdl file "D:/NIFPGA/jobs/Rw6D31z_B3Vr00M/NiFpgaMiteWriteInterface.vhd" in Library work.
Entity <NiFpgaMiteWriteInterface> compiled.
Entity <NiFpgaMiteWriteInterface> (Architecture <RTL>) compiled.
Compiling vhdl file "D:/NIFPGA/jobs/Rw6D31z_B3Vr00M/NiFpgaFifoPopBuffer.vhd" in Library work.
Entity <NiFpgaFifoPopBuffer> compiled.
Entity <NiFpgaFifoPopBuffer> (Architecture <rtl>) compiled.
Compiling vhdl file "D:/NIFPGA/jobs/Rw6D31z_B3Vr00M/NiFpgaMiteReadInterface.vhd" in Library work.
Entity <NiFpgaMiteReadInterface> compiled.
Entity <NiFpgaMiteReadInterface> (Architecture <RTL>) compiled.
Compiling vhdl file "D:/NIFPGA/jobs/Rw6D31z_B3Vr00M/TimeoutManager.vhd" in Library work.
Entity <TimeoutManager> compiled.
Entity <TimeoutManager> (Architecture <rtl>) compiled.
Compiling vhdl file "D:/NIFPGA/jobs/Rw6D31z_B3Vr00M/NiFpgaFifoClearControl.vhd" in Library work.
Entity <NiFpgaFifoClearControl> compiled.
Entity <NiFpgaFifoClearControl> (Architecture <rtl>) compiled.
Compiling vhdl file "D:/NIFPGA/jobs/Rw6D31z_B3Vr00M/NiLvToFloatingPoint.vhd" in Library work.
Entity <NiLvToFloatingPoint> compiled.
Entity <NiLvToFloatingPoint> (Architecture <rtl>) compiled.
Compiling vhdl file "D:/NIFPGA/jobs/Rw6D31z_B3Vr00M/NiLvToFixedPoint.vhd" in Library work.
Entity <NiLvToFixedPoint> compiled.
Entity <NiLvToFixedPoint> (Architecture <rtl>) compiled.
Compiling vhdl file "D:/NIFPGA/jobs/Rw6D31z_B3Vr00M/NiLvToInteger.vhd" in Library work.
Entity <NiLvToInteger> compiled.
Entity <NiLvToInteger> (Architecture <rtl>) compiled.
Compiling vhdl file "D:/NIFPGA/jobs/Rw6D31z_B3Vr00M/PkgNiFpgaIrqRegisters.vhd" in Library work.
Package <PkgNiFpgaIrqRegisters> compiled.
Compiling vhdl file "D:/NIFPGA/jobs/Rw6D31z_B3Vr00M/HandshakeBaseResetCross.vhd" in Library work.
Entity <HandshakeBaseResetCross> compiled.
Entity <HandshakeBaseResetCross> (Architecture <rtl>) compiled.
Compiling vhdl file "D:/NIFPGA/jobs/Rw6D31z_B3Vr00M/MiteDmaComponentEnableChain.vhd" in Library work.
Entity <MiteDmaComponentEnableChain> compiled.
Entity <MiteDmaComponentEnableChain> (Architecture <rtl>) compiled.
Compiling vhdl file "D:/NIFPGA/jobs/Rw6D31z_B3Vr00M/MiteDmaInput.vhd" in Library work.
Entity <MiteDmaInput> compiled.
Entity <MiteDmaInput> (Architecture <rtl>) compiled.
Compiling vhdl file "D:/NIFPGA/jobs/Rw6D31z_B3Vr00M/MiteDmaOutput.vhd" in Library work.
Entity <MiteDmaOutput> compiled.
Entity <MiteDmaOutput> (Architecture <rtl>) compiled.
Compiling vhdl file "D:/NIFPGA/jobs/Rw6D31z_B3Vr00M/NiFpgaFifoCountControl.vhd" in Library work.
Entity <NiFpgaFifoCountControl> compiled.
Entity <NiFpgaFifoCountControl> (Architecture <rtl>) compiled.
Compiling vhdl file "D:/NIFPGA/jobs/Rw6D31z_B3Vr00M/RegisterAccess32.vhd" in Library work.
Entity <RegisterAccess32> compiled.
Entity <RegisterAccess32> (Architecture <rtl>) compiled.
Compiling vhdl file "D:/NIFPGA/jobs/Rw6D31z_B3Vr00M/Adapter16.vhd" in Library work.
Entity <Adapter16> compiled.
Entity <Adapter16> (Architecture <rtl>) compiled.
Compiling vhdl file "D:/NIFPGA/jobs/Rw6D31z_B3Vr00M/DoubleSyncSlAsyncIn.vhd" in Library work.
Entity <DoubleSyncSlAsyncIn> compiled.
Entity <DoubleSyncSlAsyncIn> (Architecture <rtl>) compiled.
Compiling vhdl file "D:/NIFPGA/jobs/Rw6D31z_B3Vr00M/NiLvFloatAddCore.vhd" in Library work.
Entity <NiLvFloatAddCore> compiled.
Entity <NiLvFloatAddCore> (Architecture <rtl>) compiled.
Compiling vhdl file "D:/NIFPGA/jobs/Rw6D31z_B3Vr00M/NiLvCoerce.vhd" in Library work.
Entity <NiLvCoerce> compiled.
Entity <NiLvCoerce> (Architecture <rtl>) compiled.
Compiling vhdl file "D:/NIFPGA/jobs/Rw6D31z_B3Vr00M/MiteInterfaceOutputEnables.vhd" in Library work.
Entity <MiteInterfaceOutputEnables> compiled.
Entity <MiteInterfaceOutputEnables> (Architecture <rtl>) compiled.
Compiling vhdl file "D:/NIFPGA/jobs/Rw6D31z_B3Vr00M/RegisterAccess.vhd" in Library work.
Entity <RegisterAccess> compiled.
Entity <RegisterAccess> (Architecture <rtl>) compiled.
Compiling vhdl file "D:/NIFPGA/jobs/Rw6D31z_B3Vr00M/MiteDmaComponent.vhd" in Library work.
Entity <MiteDmaComponent> compiled.
Entity <MiteDmaComponent> (Architecture <rtl>) compiled.
Compiling vhdl file "D:/NIFPGA/jobs/Rw6D31z_B3Vr00M/MiteReadInterface.vhd" in Library work.
Entity <MiteReadInterface> compiled.
Entity <MiteReadInterface> (Architecture <RTL>) compiled.
Compiling vhdl file "D:/NIFPGA/jobs/Rw6D31z_B3Vr00M/MiteWriteInterface.vhd" in Library work.
Entity <MiteWriteInterface> compiled.
Entity <MiteWriteInterface> (Architecture <RTL>) compiled.
Compiling vhdl file "D:/NIFPGA/jobs/Rw6D31z_B3Vr00M/MiteIrq.vhd" in Library work.
Entity <MiteIrq> compiled.
Entity <MiteIrq> (Architecture <rtl>) compiled.
Compiling vhdl file "D:/NIFPGA/jobs/Rw6D31z_B3Vr00M/DoubleSyncBoolAsyncIn.vhd" in Library work.
Entity <DoubleSyncBoolAsyncIn> compiled.
Entity <DoubleSyncBoolAsyncIn> (Architecture <rtl>) compiled.
Compiling vhdl file "D:/NIFPGA/jobs/Rw6D31z_B3Vr00M/NiLvFloatAdd.vhd" in Library work.
Entity <NiLvFloatAdd> compiled.
Entity <NiLvFloatAdd> (Architecture <rtl>) compiled.
Compiling vhdl file "D:/NIFPGA/jobs/Rw6D31z_B3Vr00M/NiLvFxpAdd.vhd" in Library work.
Entity <NiLvFxpAdd> compiled.
Entity <NiLvFxpAdd> (Architecture <rtl>) compiled.
Compiling vhdl file "D:/NIFPGA/jobs/Rw6D31z_B3Vr00M/NiFpgaHostAccessibleRegister.vhd" in Library work.
Entity <NiFpgaHostAccessibleRegister> compiled.
Entity <NiFpgaHostAccessibleRegister> (Architecture <rtl>) compiled.
Compiling vhdl file "D:/NIFPGA/jobs/Rw6D31z_B3Vr00M/PkgRegister.vhd" in Library work.
Package <PkgRegister> compiled.
Package body <PkgRegister> compiled.
Compiling vhdl file "D:/NIFPGA/jobs/Rw6D31z_B3Vr00M/PkgFpgaDeviceSpecs.vhd" in Library work.
Package <PkgFpgaDeviceSpecs> compiled.
Compiling vhdl file "D:/NIFPGA/jobs/Rw6D31z_B3Vr00M/SafeBusCrossing.vhd" in Library work.
Entity <SafeBusCrossing> compiled.
Entity <SafeBusCrossing> (Architecture <rtl>) compiled.
Compiling vhdl file "D:/NIFPGA/jobs/Rw6D31z_B3Vr00M/PkgNiFpgaViControlRegister.vhd" in Library work.
Package <PkgNiFpgaViControlRegister> compiled.
Compiling vhdl file "D:/NIFPGA/jobs/Rw6D31z_B3Vr00M/MiteInterface.vhd" in Library work.
Entity <MiteInterface> compiled.
Entity <MiteInterface> (Architecture <rtl>) compiled.
Compiling vhdl file "D:/NIFPGA/jobs/Rw6D31z_B3Vr00M/NiFpgaRegFrameworkShiftReg.vhd" in Library work.
Entity <NiFpgaRegFrameworkShiftReg> compiled.
Entity <NiFpgaRegFrameworkShiftReg> (Architecture <rtl>) compiled.
Compiling vhdl file "D:/NIFPGA/jobs/Rw6D31z_B3Vr00M/NiFpgaLocalResHolderRead.vhd" in Library work.
Entity <NiFpgaLocalResHolderRead> compiled.
Entity <NiFpgaLocalResHolderRead> (Architecture <rtl>) compiled.
Compiling vhdl file "D:/NIFPGA/jobs/Rw6D31z_B3Vr00M/NiLvAdd.vhd" in Library work.
Entity <NiLvAdd> compiled.
Entity <NiLvAdd> (Architecture <rtl>) compiled.
Compiling vhdl file "D:/NIFPGA/jobs/Rw6D31z_B3Vr00M/NiFpgaLocalResHolderWrite.vhd" in Library work.
Entity <NiFpgaLocalResHolderWrite> compiled.
Entity <NiFpgaLocalResHolderWrite> (Architecture <rtl>) compiled.
Compiling vhdl file "D:/NIFPGA/jobs/Rw6D31z_B3Vr00M/NiFpgaAG_00000000_WhileLoop.vhd" in Library work.
Entity <NiFpgaAG_00000000_WhileLoop> compiled.
Entity <NiFpgaAG_00000000_WhileLoop> (Architecture <vhdl_labview>) compiled.
Compiling vhdl file "D:/NIFPGA/jobs/Rw6D31z_B3Vr00M/whileloop.vhd" in Library work.
Entity <whileloop> compiled.
Entity <whileloop> (Architecture <rtl>) compiled.
Compiling vhdl file "D:/NIFPGA/jobs/Rw6D31z_B3Vr00M/InvisibleResholder.vhd" in Library work.
Entity <InvisibleResholder> compiled.
Entity <InvisibleResholder> (Architecture <rtl>) compiled.
Compiling vhdl file "D:/NIFPGA/jobs/Rw6D31z_B3Vr00M/bushold.vhd" in Library work.
Entity <bushold> compiled.
Entity <bushold> (Architecture <rtl>) compiled.
Compiling vhdl file "D:/NIFPGA/jobs/Rw6D31z_B3Vr00M/TopEnablePassThru.vhd" in Library work.
Entity <TopEnablePassThru> compiled.
Entity <TopEnablePassThru> (Architecture <rtl>) compiled.
Compiling vhdl file "D:/NIFPGA/jobs/Rw6D31z_B3Vr00M/Interface.vhd" in Library work.
Entity <Interface> compiled.
Entity <Interface> (Architecture <rtl>) compiled.
Compiling vhdl file "D:/NIFPGA/jobs/Rw6D31z_B3Vr00M/ViControl.vhd" in Library work.
Entity <ViControl> compiled.
Entity <ViControl> (Architecture <rtl>) compiled.
Compiling vhdl file "D:/NIFPGA/jobs/Rw6D31z_B3Vr00M/DiagramReset.vhd" in Library work.
Entity <DiagramReset> compiled.
Entity <DiagramReset> (Architecture <rtl>) compiled.
Compiling vhdl file "D:/NIFPGA/jobs/Rw6D31z_B3Vr00M/ViSignature.vhd" in Library work.
Entity <ViSignature> compiled.
Entity <ViSignature> (Architecture <rtl>) compiled.
Compiling vhdl file "D:/NIFPGA/jobs/Rw6D31z_B3Vr00M/NiFpgaCtrlIndRegister.vhd" in Library work.
Entity <NiFpgaCtrlIndRegister> compiled.
Entity <NiFpgaCtrlIndRegister> (Architecture <rtl>) compiled.
Compiling vhdl file "D:/NIFPGA/jobs/Rw6D31z_B3Vr00M/CustomArbForx_ctl_0RHFpgaReadPortOnResbushold.vhd" in Library work.
Entity <CustomArbForx_ctl_0RHFpgaReadPortOnResbushold> compiled.
Entity <CustomArbForx_ctl_0RHFpgaReadPortOnResbushold> (Architecture <rtl>) compiled.
Compiling vhdl file "D:/NIFPGA/jobs/Rw6D31z_B3Vr00M/CustomArbForTopEnablesPortOnResTopEnablePassThru.vhd" in Library work.
Entity <CustomArbForTopEnablesPortOnResTopEnablePassThru> compiled.
Entity <CustomArbForTopEnablesPortOnResTopEnablePassThru> (Architecture <rtl>) compiled.
Compiling vhdl file "D:/NIFPGA/jobs/Rw6D31z_B3Vr00M/CustomArbForMiteIoLikePortOnResInterface.vhd" in Library work.
Entity <CustomArbForMiteIoLikePortOnResInterface> compiled.
Entity <CustomArbForMiteIoLikePortOnResInterface> (Architecture <rtl>) compiled.
Compiling vhdl file "D:/NIFPGA/jobs/Rw6D31z_B3Vr00M/NiFpgaAG_Untitled_2.vhd" in Library work.
Entity <NiFpgaAG_Untitled_2> compiled.
Entity <NiFpgaAG_Untitled_2> (Architecture <vhdl_labview>) compiled.
Compiling vhdl file "D:/NIFPGA/jobs/Rw6D31z_B3Vr00M/TheWindow.vhd" in Library work.
Entity <TheWindow> compiled.
Entity <TheWindow> (Architecture <behavioral>) compiled.
Compiling vhdl file "D:/NIFPGA/jobs/Rw6D31z_B3Vr00M/toplevel_gen.vhd" in Library work.
Entity <toplevel_gen> compiled.
Entity <toplevel_gen> (Architecture <vhdl_modgen>) compiled.
FATAL_ERROR:Xst:Portability/export/Port_Main.h:143:1.17 - This application has discovered an exceptional condition from which it cannot recover. Process will terminate. For technical support on this issue, please open a WebCase with this project attached at http://www.xilinx.com/support.

Process "Synthesis" failed

 

I request your help on resolving this issue. 

 

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2 Replies
vijayak
Xilinx Employee
Xilinx Employee
2,736 Views
Registered: ‎10-24-2013

Hi @gajanan

This looks to be crash. Which version of ISE are you using?

If not the latest, try using 14.7 see if that helps.

Thanks,Vijay
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vuppala
Xilinx Employee
Xilinx Employee
2,725 Views
Registered: ‎04-16-2012

Hi @gajanan

 

From the log file, it looks like the issue is with toplevel_gen module. Check this module for syntax issues as fatal error occurred while compiling this module.

 

Thanks,

Vinay 

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