05-10-2017 02:14 PM
I have designed wrapper for wishbone slave interface and MIG DDR3 SDRAM User interface for FPGA 7 series Artix. In simulations (Test Bench) it is working fine wishbone send's ten different data's for writing and read's the same ten data accurately everything is perfect and smooth. Moreover my wrapper is synthesized it has no critical warnings or errors. I have created top module which consists of my wrapper and MIG user interface. When ever I synthesize top module the ok status is ticked but has some critical warnings from MIG. whenever I implement my code on FPGA , It doesn't work. My supervisor confirmed that he has used other wrapper with same MIG and it is working fine. What can be the possible reason, does reset (asynchronous/synchronous) has effect on hardware implementation. Below I have attached my code along with images regarding errors,schematic and status of my top module.
05-10-2017 04:08 PM
@sarmad_wahab It seems like you have all that you need to fix your problem. You need to go through the critical warnings and clean them up. Then run your simulations again but use the timing annotated implementation level netlist for your own IP instead of the RTL version and debug to see why it doesn't work (so testbench and MIG stay the same but the wrapper uses the implementation netlist). Just dumping your code here is probably not going to be very productive.
05-10-2017 04:37 PM