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aminemr
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Registered: ‎01-14-2015

FPGA: i get a different answer in modelsim and in device

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I'm new to VHDL and require some help. I'm Interfacing with Artix 7 to make a simple modular multiplier but i have some problems. When I synthesize my code i get some warnings which i think are wrong so i ignored them. when I run post route simulation i got the results as required but when i burned the code on hardware i get a different answer for the same value that i check in the stimulus.

Can some one please help me.

 

the warnings that i get are:

 

Xst:737 - Found 1-bit latch for signal <zt<1>>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.

 

Xst:1710 - FF/Latch <C_b_out_30> (without init value) has a constant value of 0 in block <Montgomery_multiplier>. This FF/Latch will be trimmed during the optimization process.

 

Xst:1895 - Due to other FF/Latch trimming, FF/Latch <z8_19> (without init value) has a constant value of 0 in block <Montgomery_multiplier>. This FF/Latch will be trimmed during the optimization process.

 

Xst:3001 - This design contains one or more registers or latches with an active
asynchronous set and asynchronous reset. While this circuit can be built,
it creates a sub-optimal implementation in terms of area, power and
performance. For a more optimal implementation Xilinx highly recommends
one of the following:
1) Remove either the set or reset from all registers and latches if
not needed for required functionality
2) Modify the code in order to produce a synchronous set
and/or reset (both is preferred)
3) Use the -async_to_sync option to transform the asynchronous
set/reset to synchronous operation
(timing simulation highly recommended when using this option)

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aher
Xilinx Employee
Xilinx Employee
1,941 Views
Registered: ‎07-21-2014

Hi,

 

as message indicates, do you have any latch in the synthesized/implemented design? you can see this in the synthesized design schematic.

if you have latches try to see which part of code is responsible for it and most probably try to complete your case/if statements accordingly.

 

also if you have asynchronous set/reset, make it synchronous.

 

thanks,

Shreyas

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aher
Xilinx Employee
Xilinx Employee
1,942 Views
Registered: ‎07-21-2014

Hi,

 

as message indicates, do you have any latch in the synthesized/implemented design? you can see this in the synthesized design schematic.

if you have latches try to see which part of code is responsible for it and most probably try to complete your case/if statements accordingly.

 

also if you have asynchronous set/reset, make it synchronous.

 

thanks,

Shreyas

----------------------------------------------------------------------------------------------
Try to search answer for your issue in forums or xilinx user guides before you post a new thread.

Kindly note- Please mark the Answer as "Accept as solution" if information provided solves your query.
Give Kudos (star provided in right) to a post which you think is helpful and reply oriented.
----------------------------------------------------------------------------------------------

View solution in original post

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