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Observer
Observer
3,592 Views
Registered: ‎12-21-2016

First post , work with FFT

Hi 

This is my first post in this community , i'm so glad for join such a great community forum for a great company . 

Here i wanna ask about some problems i have in my design for FFT processing on FPGA . I'm still a beginner with FFT and HDL language , and i'm trying to design an FFT core taking the spectrum of a sampled data comes from XADC core . 

So far my ADC looks working successfully , but i have a mistake with FFT core and most probably its because of data valid line . Can you help me and tell me how can i control this line perfectly for every new data comes from the ADC ? Cuz i tried to set it high always but it failed unfortunately . So please may you tell a good way to control this line and my FFT core . 

Note that i'm using the maximum samling freq which is about 1MSPS with DRP mode . 

I hope if someone can help me , i will appreciate that too much . 

 

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Xilinx Employee
Xilinx Employee
3,583 Views
Registered: ‎08-01-2008

Welcome aboard!
You can try FFT Streaming architecture for continuous data , You may use simulation first . the Demo testbench provided with core
Thanks and Regards
Balkrishan
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Observer
Observer
3,573 Views
Registered: ‎12-21-2016

Thanks sir

I already using streaming I/O architecture for my design cuz im working in real time mode .

But i'm wondering should i assert s_axis_tdata_valid line always high , or how should i assert it to tell the core there is data coming from ADC correctly .

 

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