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pkorrapati
Visitor
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Registered: ‎03-11-2016

Help: VFIFO and MIG with XADC - KINTEX 7

I'm trying to use the DDR3 RAM as a buffer for a single channel data acquisition from the XADC using the virtual FIFO controller.

I set up the VFIFO with a burst mode of 4096 Bytes and allocated 8192 4K pages which should give me 32MB; technically I should be able to store 8 Mega Samples of size 32 bits each in my memory.

But the VFIFO reports it is full on 8100 samples. This number changes with the number of 4K Pages allocated for the channel and is always very close the number of allocated 4K pages. Does anyone know how to solve this issue?

Development Board: Genesys2 with Kintex 7 FPGA
Vivado version: 2014.4
XADC 3.0
VFIFO 2.0

Structure:
XADC->AXI4-Stream Interconnect->VFIFO->MIG

I'm using a GPIO to read the status of the VFIFO.

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austin
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Registered: ‎02-27-2008

per the data sheet on the VFIFO core,

 

The full is asserted some blocks before it is actually full.  Look at the table defining the signal's behavior.

 

 

Austin Lesea
Principal Engineer
Xilinx San Jose
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pkorrapati
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Registered: ‎03-11-2016

Thanks for the reply Austin. I agree that the data sheet says that the full is asserted 8 beats before the memory is actually full, but that is not the issue that Im facing.

 

On further reading through the document, I came across the 'Design Parameters' table, which reads "If axis_tdata_width is 32, burst sizes of 512 and 1024 are allowed". Apparantly, as soon as you add VFIFO ip in Vivado 2014.4, it lets you select 4096 as the burst size, but when you change the data width to another value and back to 32, it shows only 512 and 1024 burst sizes.

 

I corrected my settings to the following:

 

On the VFIFO, I set axis_tdata_width to 32 bits, burst size of 1024. I have the basic 2 Channel configuration (but I'm using only 1 channel) with 8192 4K pages; giving me 32 MB of space per channel.

 

MIG is configured at 32 bit data width. The DDR is configured to 1G memory.

 

I still am not able to fill up the available memory. When it fills data of 128KB, I get a signal that the VFifo is full. Atleast its an improvement compared to the previous 32KB that I was able to store (8100 Samples of 32 bit each). Any ideas?

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austin
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Registered: ‎02-27-2008

p,

 

One other thought I had was that some widths and depths are more efficient in using the BRAM than others.  And, I am unsure if it is even using it in FIFO-BRAM mode.  I suspect the most efficient use is to keep all widths at 32 bits.  But having 4 8 bit wide VFIFO vs. 1 32 bit wide VFOFO probably does use BRAM resources differenty (?).

 

4096 bytes is one BRAM (fits in a 36kb BRAM as 4096 bytes).

 

4096 32 bit words would then require 4 BRAMs....could be the core is not set up to be that deep (hence the 1024 allowed).

 

Austin Lesea
Principal Engineer
Xilinx San Jose
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martinthompson
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Registered: ‎08-14-2007

If it's any consolation, I too am seeing this behaviour... My observation so far is that it seems to depend on how the incoming bursts align with the outgoing bursts. 

Martin Thompson
martin.j.thompson@trw.com
http://www.conekt.co.uk/capabilities/electronic-hardware
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xiange
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Registered: ‎01-03-2013

My understanding is that vfifo stores incoming data in DDR in form of "bins" where the size of each bin equals to the burst size (4096,2048,1024 or 512bytes). If it sees the burst is broken, it moves onto the next bin available.

 

According to PG038,

 

Burst size is broken under the following conditions:
° When MM address crosses 4 K boundary.
° On determining channel change within the burst
° On detecting a timeout (tvalid deasserted for 256-clocks for the burst)

 

I think the last two conditions may expel a lot of myths.

 

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