12-17-2016 04:20 AM
12-18-2016 04:07 AM
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12-17-2016 06:51 AM - edited 12-17-2016 06:54 AM
Did you include this line in your code: use IEEE.STD_LOGIC_UNSIGNED.ALL;
Try with this code:
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
use IEEE.NUMERIC_STD.ALL;
entity contador is
Port ( clk : in STD_LOGIC;
rst : in STD_LOGIC;
cnt_out : out STD_LOGIC_VECTOR (3 downto 0));
end contador;
architecture Behavioral of contador is
signal cnt: STD_LOGIC_VECTOR (3 downto 0):="0000";
begin
process (clk,rst,cnt)
begin
if rst='1' then cnt<="0000";
elsif
rising_edge (clk) then
cnt<= cnt + '1';
end if;
end process;
cnt_out<=cnt;
end Behavioral;
12-17-2016 08:58 PM
Hi @50081647,
When predefined VHDL functions are used, the appropriate IEEE library must be defined. For example, this error will occur if any of the operators (+, -, *, =, <=, etc.) in the std_logic_unsigned library are used on std_logic_vector inputs without the following lines existing in the VHDL header:
library IEEE;
use IEEE.std_logic_unsigned.all;
Generally, be sure to use the correct IEEE library for the function you wish to call. The library might differ depending upon the type of operands used. For example, the std_logic_unsigned library is correct for the "+" operator if the operands are of std_logic_vector or integer type, but you should use the std_logic_arith library if the inputs are any combination of signed, unsigned, integer, or std_ulogic. Examine the libraries themselves to determine which should be used for your particular case.
The above error message can also occur if the operand has not been properly declared:
a <= b when (c= '1') else 'Z';
If signal "c" is not declared, then XST will issue the error message. Once "c" is declared, the error message will go away.
Thanks,
Sarada
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12-18-2016 02:10 AM
12-18-2016 04:07 AM
Is your original query related to this thread addressed?
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