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Visitor
Visitor
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Registered: ‎10-15-2016

Hi, my program does not work. it's simple

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Hi, my program does not work. it's simple ERROR:HDLParsers:808 - "C:/Users/fer/Desktop/proyectos ISE 14.7/contador/contador.vhd" Line 47. + can not have such operands in this context. entity contador is Port ( clk : in STD_LOGIC; rst : in STD_LOGIC; cnt_out : out STD_LOGIC_VECTOR (3 downto 0)); end contador; architecture Behavioral of contador is signal cnt: STD_LOGIC_VECTOR (3 downto 0):="0000"; begin process (clk,rst,cnt) begin if rst='1' then cnt<="0000"; elsif rising_edge (clk) then cnt<= cnt + '1'; end if; end process; cnt_out<=cnt; end Behavioral Thank you
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Moderator
Moderator
6,757 Views
Registered: ‎06-24-2015

@50081647,

 

Is your original query related to this thread addressed?

If yes, please close this thread by marking appropriate answer as "Accept as Solution"

And please create a new thread for a different query.

Thanks,
Nupur
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Moderator
Moderator
3,652 Views
Registered: ‎06-24-2015

@50081647,

Did you include this line in your code: use IEEE.STD_LOGIC_UNSIGNED.ALL;

 

Try with this code:

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
use IEEE.NUMERIC_STD.ALL;

 

entity contador is
Port ( clk : in STD_LOGIC;
rst : in STD_LOGIC;
cnt_out : out STD_LOGIC_VECTOR (3 downto 0));
end contador;
architecture Behavioral of contador is
signal cnt: STD_LOGIC_VECTOR (3 downto 0):="0000";
begin
process (clk,rst,cnt)
begin
if rst='1' then cnt<="0000";
elsif
rising_edge (clk) then
cnt<= cnt + '1';
end if;
end process;
cnt_out<=cnt;
end Behavioral;

Thanks,
Nupur
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Explorer
Explorer
3,620 Views
Registered: ‎10-14-2015

Hi @50081647,

 


When predefined VHDL functions are used, the appropriate IEEE library must be defined. For example, this error will occur if any of the operators (+, -, *, =, <=, etc.) in the std_logic_unsigned library are used on std_logic_vector inputs without the following lines existing in the VHDL header: 
 

library IEEE; 

use IEEE.std_logic_unsigned.all; 

 
Generally, be sure to use the correct IEEE library for the function you wish to call. The library might differ depending upon the type of operands used. For example, the std_logic_unsigned library is correct for the "+" operator if the operands are of std_logic_vector or integer type, but you should use the std_logic_arith library if the inputs are any combination of signed, unsigned, integer, or std_ulogic. Examine the libraries themselves to determine which should be used for your particular case.
 
The above error message can also occur if the operand has not been properly declared: 

a <= b when (c= '1') else 'Z'; 

 If signal "c" is not declared, then XST will issue the error message. Once "c" is declared, the error message will go away.

 

Thanks,

Sarada

 

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Visitor
Visitor
3,602 Views
Registered: ‎10-15-2016

Hi, I have a 2 basys card and it has a bridge to select the frequency 100MhZ 50 MHZ and 25 MH but I do not understand how the bridge is placed. You can also put a I.C. Which I.C is placed ?.

thank you

 

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Moderator
Moderator
6,758 Views
Registered: ‎06-24-2015

@50081647,

 

Is your original query related to this thread addressed?

If yes, please close this thread by marking appropriate answer as "Accept as Solution"

And please create a new thread for a different query.

Thanks,
Nupur
--------------------------------------------------------------------------------------------
Google your question before posting. If someone's post answers your question, mark the post as answer with "Accept as solution". If you see a particularly good and informative post, consider giving it Kudos (click on the 'thumbs-up' button).

View solution in original post

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