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4,707 Views
Registered: ‎11-03-2013

How to deselect XST option ISE 12.4 and synthesize

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Hello I want to deselect XST option in ISE 12.4 as I am getting an error about port 1 of <inst_name> is connected to GND.

Regards,

jeevanreddymandali
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Xilinx Employee
Xilinx Employee
5,979 Views
Registered: ‎09-20-2012

Hi,

 

Check in RTL how the inputs and outputs of this BUFG "init_clk_ibufg_i" are connected.

 

Thanks,

Deepika.

Thanks,
Deepika.
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Xilinx Employee
Xilinx Employee
4,703 Views
Registered: ‎09-20-2012

Hi,

 

Can you copy paste the complete error message?

 

Which XST option do you want to disable?

 

Thanks,

Deepika.

Thanks,
Deepika.
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Xilinx Employee
Xilinx Employee
4,690 Views
Registered: ‎07-11-2011

Hi,

 

Port 1 of <inst_name> is connected to GND

>> Can be a valid error or warning, it generally arises when your deisgn has some signals/ports that have no transitions.

For example if you you declare a 7 bit counter and run it only till 32 only 5 bits will be used the rest will be always stuck to ground.

 

You should check if the error is valid for your design in which case you can ignore it .

 

Deselecting XST might not be an option to resolve it

 

Hope this helps

 

Regards,

Vanitha.

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4,689 Views
Registered: ‎11-03-2013

Okay, this is the actual error. I donot know which XST option I want to deselect. While I was trying searching this error in google I got an answer suggesting me to turn off the XST and synthesize, So, I started giving it a try.

Mapping all equations...
ERROR:Xst:2033 - Port I of Input buffer Inst_aurora1/reset_logic_i/init_clk_ibufg_i is connected to GND
ERROR:Xst:2033 - Port I of Input buffer Inst_aurora2/reset_logic_i/init_clk_ibufg_i is connected to GND
ERROR:Xst:1847 - Design checking failed
Process "Synthesize - XST" failed

Regards,

jeevanreddymandali
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Xilinx Employee
Xilinx Employee
4,685 Views
Registered: ‎02-06-2013

Hi

 

Check if you are using a BUFIO external to the core as there will be a BUFIO 

already in the core, which causes this error.

 

To resolve this problem, remove the BUFIO instantiation outside the core. 

Regards,

Satish

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Xilinx Employee
Xilinx Employee
5,980 Views
Registered: ‎09-20-2012

Hi,

 

Check in RTL how the inputs and outputs of this BUFG "init_clk_ibufg_i" are connected.

 

Thanks,

Deepika.

Thanks,
Deepika.
--------------------------------------------------------------------------------------------
Google your question before posting. If someone's post answers your question, mark the post as answer with "Accept as solution". If you see a particularly good and informative post, consider giving it Kudos (the star on the left)

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Xilinx Employee
Xilinx Employee
4,651 Views
Registered: ‎09-20-2012

Hi,

 

As discussed in the other thread http://forums.xilinx.com/t5/Virtex-Family-FPGAs/How-to-create-a-black-box-NGC-file-by-writing-a-module-that/m-p/388163#M17973 , this issue is due to buffer in top level driving IBUFG in the core. You need to either remove the IBUFG inside the core or directly connect it to port in top level.

 

Thanks,

Deepika.

Thanks,
Deepika.
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