Interfacing ported design on FPGA - Virtex 5- XC5VLX50t with host computer to measure its performance
I have my design ready to be ported onto the FPGA- XC5VLX50T.
However, I need to control the start signal and drive the seed to the design(start and seed are I/O ports of my top module) via my host computer and read back all the generated outputs per clock cycle until the desired count is achieved. My design is running at 200Mhz.
I am guessing I should be using onchip microprocessor for doing this, but how to do so is the next big question.
Please suggest me a solution.
Any documents/tutorials/examples/PDFs are very much appreciated.