UPGRADE YOUR BROWSER

We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

cancel
Showing results for 
Search instead for 
Did you mean: 
Highlighted
Visitor swethach
Visitor
1,576 Views
Registered: ‎02-21-2014

Interfacing ported design on FPGA - Virtex 5- XC5VLX50t with host computer to measure its performance

Hi,

 

I have my design ready to be ported onto the FPGA- XC5VLX50T.

However, I need to control the start signal and drive the seed to the design(start and seed are I/O ports of my top module) via my host computer and read back all the generated outputs per clock cycle until the desired count is achieved. My design is running at 200Mhz.

 

I am guessing I should be using onchip microprocessor for doing this, but how to do so is the next big question.

 

Please suggest me a solution.

 

Any documents/tutorials/examples/PDFs are very much appreciated.

 

Thanks

0 Kudos