UPGRADE YOUR BROWSER

We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

Reply
Visitor
Posts: 18
Registered: ‎07-07-2014
Accepted Solution

JTAG pin constraints in VC707

Hi,

 

We are trying to implement ARC EM6 processor with JTAG interface on VC707 Evaluation board.

In this design we want to connect JTAG connection from ARC EM6 processor to JTAG pins of FPGA.

we are unable to find the pin locations of JTAG.

 

Can any one help us.

 

Thanks

UK


Accepted Solutions
Moderator
Posts: 1,258
Registered: ‎07-23-2015

Re: JTAG pin constraints in VC707

@ushakiran1989 The JTAG pins of FPGA are dedicated pins. You cannot connect your ARC EM6 processor JTAG signals to the dedicated JTAG pins of FPGA i.e. you cannot constraint them in XDC file. 

 

You will need to route them to GPIO and use them 

 

 

--------------------------------------------------------------------------------------------------------------------
There's no such thing as a stupid question. Feel free to ask but do a quick search to make sure it ain't already answered.
Keep conversing, give Kudos and Accept Solution when you get one.
-----------------------------------------------------------------------------------------------------------------------

View solution in original post


All Replies
Scholar
Posts: 3,000
Registered: ‎06-05-2013

Re: JTAG pin constraints in VC707

@ushakiran1989 I am not sure what you are trying to do but here is what you are looking for

https://www.xilinx.com/support/packagefiles/v7packages/xc7vx485tffg1761pkg.txt

 

P10   TCK_0                         NA                 0                  NA            NA                  CONFIG    NA
P11   TMS_0                         NA                 0                  NA            NA                  CONFIG    NA
R10   TDO_0                         NA                 0                  NA            NA                  CONFIG    NA
T10   TDI_0              

 

-Pratham

----------------------------------------------------------------------------------------------
Kindly note- Please mark the Answer as "Accept as solution" if information provided is helpful.

Give Kudos to a post which you think is helpful and reply oriented.
----------------------------------------------------------------------------------------------
Moderator
Posts: 1,258
Registered: ‎07-23-2015

Re: JTAG pin constraints in VC707

@ushakiran1989 The JTAG pins of FPGA are dedicated pins. You cannot connect your ARC EM6 processor JTAG signals to the dedicated JTAG pins of FPGA i.e. you cannot constraint them in XDC file. 

 

You will need to route them to GPIO and use them 

 

 

--------------------------------------------------------------------------------------------------------------------
There's no such thing as a stupid question. Feel free to ask but do a quick search to make sure it ain't already answered.
Keep conversing, give Kudos and Accept Solution when you get one.
-----------------------------------------------------------------------------------------------------------------------