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Participant vazquez
Participant
4,485 Views
Registered: ‎10-10-2007

Kintex GT - Reference clock routing to adjacent QUADs fails in placemet

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Hi newsgroup,

 

on a Kintex-7 design I am getting the following error message in Vivado 2015.1:

 

[Place 30-512] Clock region assignment has failed. Clock buffer 'g_CAT_GTRefclks[0].i_ibufds' (IBUFDS_GTE2) is placed at site IBUFDS_GTE2_X0Y8 in CLOCKREGION_X1Y4. Its loads need to be placed in the area enclosed by clock regions CLOCKREGION_X1Y4 and CLOCKREGION_X1Y4. One of its loads 'g_CAT.i_qfab/g_Quads[7].i_quad/U0/transceiver_inst/gtwizard_inst/U0/GTWIZARD_i/gt0_GTWIZARD_i/gtxe2_i' (GTXE2_CHANNEL) is placed in site GTXE2_CHANNEL_X0Y12 in CLOCKREGION_X1Y3 which is outside the permissible area.

 

I have found AR#60258

http://www.xilinx.com/support/answers/60258.html

 

It is said to be a known issue and to be resolved in 2014.2.

 

Has this issue only been fixed for Artix-7 devices?

 

Rgds, vazquez

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Xilinx Employee
Xilinx Employee
8,465 Views
Registered: ‎09-20-2012

Re: Kintex GT - Reference clock routing to adjacent QUADs fails in placemet

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Hi @vazquez

 

I see that the IBUFDS_GTE2 is driving the TXUSRCLK and TXUSRCLK2 pins of the GT_CHANNEL instances directly. In general it is recommended to drive these pins from BUFG to have minimal skew between them. 

 

Refer to page-109 "TXUSRCLK and TXUSRCLK2 generation" of http://www.xilinx.com/support/documentation/user_guides/ug476_7Series_Transceivers.pdf

 

Thanks,

Deepika.

Thanks,
Deepika.
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Xilinx Employee
Xilinx Employee
4,476 Views
Registered: ‎09-20-2012

Re: Kintex GT - Reference clock routing to adjacent QUADs fails in placemet

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Hi @vazquez

 

How many GT instances is this IBUFDS_GTE2 instance driving? Are they within 3 adjacent clock regions?

 

Can you attach the _opt.dcp located at .runs-->impl_1 folder?

 

Thanks,

Deepika.

Thanks,
Deepika.
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Participant vazquez
Participant
4,461 Views
Registered: ‎10-10-2007

Re: Kintex GT - Reference clock routing to adjacent QUADs fails in placemet

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>How many GT instances is this IBUFDS_GTE2 instance driving?

 

The IBFUDS_GTE2 instance is driving 19 other GT instances (total of 20 QSGMII-IP-Core instances).

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Xilinx Employee
Xilinx Employee
4,458 Views
Registered: ‎09-20-2012

Re: Kintex GT - Reference clock routing to adjacent QUADs fails in placemet

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Hi @vazquez

 

These rules must be observed when sharing a reference clock to ensure that jitter margins for high-speed designs are met:

• The number of Quads above the sourcing Quad must not exceed one.

• The number of Quads below the sourcing Quad must not exceed one.

• The total number of Quads sourced by an external clock pin pair (MGTREFCLKN/ MGTREFCLKP) must not exceed three Quads (or 12 transceivers).

 

It looks like you are not following 3rd point above. Please modify your design to satisfy this requirement.

 

Thanks,

Deepika.

Thanks,
Deepika.
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Participant vazquez
Participant
4,450 Views
Registered: ‎10-10-2007

Re: Kintex GT - Reference clock routing to adjacent QUADs fails in placemet

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I am connecting an external clock pin pair (MGTREFCLKN/ MGTREFCLKP) to an IBUFDS_GTE2. The output of that I connect

to a BUFG to drive all the GMII-TX-Interfaces of the 20 QSGMII-IP-Cores.

 

The GTRefClk-Inputs of 4 QSGMII-IP-Cores are driven by one clock pin pair (MGTREFCLKN/ MGTREFCLKP). So there is a total number of 5 clock pin pairs (MGTREFCLKN/ MGTREFCLKP) to drive 20 QSGMII GTRefClks. And clock pin pair number 0 is driving (by BUFG as stated above) all GMII-TX-Interfaces (to have exactly one tx user clock in my design). The 5 external clocks are distributed by an external clock distribution chip.

 

In "ug472_7Series_Clocking.pdf" the following statement can be found:

"BUFGs do not belong to a clock region and can reach any clocking point on the device."

 

So does the restriction No.3 you mentioned apply to my design?

 

Regards, vazquez

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Xilinx Employee
Xilinx Employee
4,447 Views
Registered: ‎09-20-2012

Re: Kintex GT - Reference clock routing to adjacent QUADs fails in placemet

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Hi @vazquez

 

As per my knowledge the MGTREFCLK pins of GT instances should be directly driven by IBUFDS_GTE2 primitive (you can drive it from BUFG).

 

Can you attach the _opt.dcp file?

 

Thanks,

Deepika.

 

Thanks,
Deepika.
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Participant vazquez
Participant
4,442 Views
Registered: ‎10-10-2007

Re: Kintex GT - Reference clock routing to adjacent QUADs fails in placemet

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>As per my knowledge the MGTREFCLK pins of GT instances should be directly driven by IBUFDS_GTE2

 

No, only the GMII-TX interfaces are driven by MGTREFCLK(0) -> IBUFDS_GETES -> BUFG

 

The .dcp file has 16MB.

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Participant vazquez
Participant
4,433 Views
Registered: ‎10-10-2007

Re: Kintex GT - Reference clock routing to adjacent QUADs fails in placemet

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QSGMII_clocks_distribution.GIF

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Xilinx Employee
Xilinx Employee
4,423 Views
Registered: ‎09-20-2012

Re: Kintex GT - Reference clock routing to adjacent QUADs fails in placemet

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Hi @vazquez

 

I will send you ezmove package where you can upload the DCP file.

 

Thanks,

Deepika.

Thanks,
Deepika.
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Xilinx Employee
Xilinx Employee
8,466 Views
Registered: ‎09-20-2012

Re: Kintex GT - Reference clock routing to adjacent QUADs fails in placemet

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Hi @vazquez

 

I see that the IBUFDS_GTE2 is driving the TXUSRCLK and TXUSRCLK2 pins of the GT_CHANNEL instances directly. In general it is recommended to drive these pins from BUFG to have minimal skew between them. 

 

Refer to page-109 "TXUSRCLK and TXUSRCLK2 generation" of http://www.xilinx.com/support/documentation/user_guides/ug476_7Series_Transceivers.pdf

 

Thanks,

Deepika.

Thanks,
Deepika.
--------------------------------------------------------------------------------------------
Google your question before posting. If someone's post answers your question, mark the post as answer with "Accept as solution". If you see a particularly good and informative post, consider giving it Kudos (the star on the left)

View solution in original post

Participant vazquez
Participant
2,735 Views
Registered: ‎10-10-2007

Re: Kintex GT - Reference clock routing to adjacent QUADs fails in placemet

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Thank you very much. Although drawn the BUFG connection in my diagram I had not made the correct BUFG connection in my HDL code.

 

 

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