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Visitor herwis
Visitor
5,064 Views
Registered: ‎02-05-2012

LVDS_IO Spartan 3e

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Hi,

I need  to use LVDSIO in spartans 3e. My idea about lvdsio it has 2 inputs p & n and 1 output so we can use it with the buffer as a comparator. I was reading the guid when i found the code below for instantaiting the LVDSIO . the problem it has different input output form.  Any idea ?!!! see the pic for more details.LVDS.png

 

library IEEE;
use IEEE.std_logic_1164.all;
-- library unisim;
-- use unisim.vcomponents.all;
entity LVDSIO is
port (
CLK, DATA, Tin : in STD_LOGIC;
IODATA_p, IODATA_n : inout STD_LOGIC;
Q_p, Q_n : out STD_LOGIC
);
end LVDSIO;
architecture BEHAV of LVDSIO is
-- remove the following component declarations
-- if using XST or synplify
component IBUF_LVDS is port (
I : in STD_LOGIC;
O : out STD_LOGIC
);
end component;
component OBUF_LVDS is port (
I : in STD_LOGIC;
O : out STD_LOGIC
);
end component;
component IOBUF_LVDS is port (
I : in STD_LOGIC;
T : in STD_LOGIC;
IO : inout STD_LOGIC;
O : out STD_LOGIC
);
end component;
component INV is port (
I : in STD_LOGIC;
O : out STD_LOGIC
);

end component;
component IBUFG_LVDS is port(
I : in STD_LOGIC;
O : out STD_LOGIC
);
end component;
component BUFG is port(
I : in STD_LOGIC;
O : out STD_LOGIC
);
end component;
signal iodata_in : std_logic;
signal iodata_n_out : std_logic;
signal iodata_out : std_logic;
signal DATA_int : std_logic;
signal Q_p_int : std_logic;
signal Q_n_int : std_logic;
signal CLK_int : std_logic;
signal CLK_ibufgout : std_logic;
signal Tin_int : std_logic;
begin
UI1: IBUF_LVDS port map (
I => DATA,
O => DATA_int
);
UI2: IBUF_LVDS port map (
I => Tin,
O => Tin_int
);
UO_p: OBUF_LVDS port map (
I => Q_p_int,
O => Q_p
);
UO_n: OBUF_LVDS port map (
I => Q_n_int,
O => Q_n
);
UIO_p: IOBUF_LVDS port map (
I => iodata_out,
T => Tin_int,IO => iodata_p,
O => iodata_in
);
UIO_n: IOBUF_LVDS port map (
I => iodata_n_out,
T => Tin_int,
IO => iodata_n,
O => open
);
UINV: INV port map (
I => iodata_out,
O => iodata_n_out
);
UIBUFG: IBUFG_LVDS port map (
I => CLK,
O => CLK_ibufgout
);

UBUFG: BUFG port map (
I => CLK_ibufgout,
O => CLK_int
);
My_D_Reg: process (CLK_int, DATA_int)
begin
if (CLK_int'event and CLK_int='1') then
Q_p_int <= DATA_int;
end if;
end process; -- End My_D_Reg
iodata_out <= DATA_int and iodata_in;
Q_n_int <= not Q_p_int;
end BEHAV;

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1 Solution

Accepted Solutions
Instructor
Instructor
6,363 Views
Registered: ‎08-14-2007

Re: LVDS_IO Spartan 3e

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You're making this way too complex.

 

Look in the Libraries guide for IOBUFDS

 

-- Gabor

-- Gabor
4 Replies
Instructor
Instructor
6,364 Views
Registered: ‎08-14-2007

Re: LVDS_IO Spartan 3e

Jump to solution

You're making this way too complex.

 

Look in the Libraries guide for IOBUFDS

 

-- Gabor

-- Gabor
Visitor herwis
Visitor
5,052 Views
Registered: ‎02-05-2012

Re: LVDS_IO Spartan 3e

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Thank you so much. i really appreciate.

I have two more questions if u can help me.

 

first  what difference will it make setting the DIFF_TERM => true or false.  i know it will enable the built_in differential termination resistor but what difference will it make ?

 

Second is it possible to send analog data as two input sin wave to the input of the LVDS_IO?

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Teacher eteam00
Teacher
5,045 Views
Registered: ‎07-21-2009

Re: LVDS_IO Spartan 3e

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...i know it will enable the built_in differential termination resistor but what difference will it make ?

 

What sort of difference might be important to you?

 

If you want to use differential inputs to a Spartan-3e as a comparator because you don't want to spend $.30 ($.10 or less in volume) on an LM339 quad comparator, you will have no problems from me.

 

The answer is yes, you can do this, as long as you do not violate the datasheet maximum ratings for input voltage.  You also need to respect the datasheet common-mode voltage tolerance range, for meaningful result.

 

As for whether or not the internal differential termination resistor will affect your circuit -- this depends on the characteristics of the source signal (including output impedance and voltage).  Why not buy an inexpensive Spartan-3e Starter Kit board and experiment with it?

 

While you're experimenting with this, have you considered using another IO pin to provide hysteresis (i.e. schmitt trigger) for your comparator configuration?

 

-- Bob Elkind

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Highlighted
4,333 Views
Registered: ‎03-09-2014

Re: LVDS_IO Spartan 3e

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hi,

could you give me full project with there component, i need to simulate how data transfer between ADc and fpga by using lvds.

many thanks!

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