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dabell-cc
Visitor
Visitor
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Registered: ‎01-18-2013

LVDS differential pairs for ISE 14.4 and the Spartan-3E

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Hello folks,

 

I'm trying to set up a project with a couple LVDS lines and it's proving frustrating.

 

I had expected functionality similar to this: http://www.vhdl.us/SecondEdition_unrestricted/Pedroni_ExtraMaterial_Using_LVDS_pins_v1.pdf

I had expected to declare an input signal of

 

input : in std_logic;

 and then be able to link that to an appropriate input buffer that will turn the LVDS input into std_logic behind the scenes for me. 

 

I'm sure there's a really good how-to or user guide somewhere, but I cannot find it for the life of me.

So here are my questions:

 

Do I need to declare both a true and negated signal in my port list?

 

If that's a yes are they correct to be std_logic? 

I know _P and _N are common suffixes, but are they necessary for the tools to correctly identify the pairs?

 

Any help in this is appreciated!

 

Thanks in advance,

dabell

 

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mcgett
Xilinx Employee
Xilinx Employee
10,425 Views
Registered: ‎01-03-2008

Differential input and output buffers must be instantiated in your code as an IBUFDS or an OBUFDS.  They can not be inferred.  Your top level port declaration most include both a P and N port to connect to the IBUFDS I and IB ports or the OBUFDS O & OB ports.    The output port from the IBUFDS and the input port from the OBUFDS would be a single std_logic signal.

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mcgett
Xilinx Employee
Xilinx Employee
10,426 Views
Registered: ‎01-03-2008

Differential input and output buffers must be instantiated in your code as an IBUFDS or an OBUFDS.  They can not be inferred.  Your top level port declaration most include both a P and N port to connect to the IBUFDS I and IB ports or the OBUFDS O & OB ports.    The output port from the IBUFDS and the input port from the OBUFDS would be a single std_logic signal.

------Have you tried typing your question into Google? If not you should before posting.
Too many results? Try adding site:www.xilinx.com

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dabell-cc
Visitor
Visitor
7,993 Views
Registered: ‎01-18-2013
Great, thank you!

I just looked through the top4_rx.vhd file from xapp485.zip and noticed that. (For people looking for examples in the future).

O and OB ports seem to be std_logic in this code, is that the standard?

Much appreciated,
dabell
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mcgett
Xilinx Employee
Xilinx Employee
7,988 Views
Registered: ‎01-03-2008

> O and OB ports seem to be std_logic in this code, is that the standard?

 

All ports of Xilinx VHDL components are defined as std_logic or std_logic_vector.

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bassman59
Historian
Historian
7,987 Views
Registered: ‎02-25-2008

@dabell-cc wrote:

O and OB ports seem to be std_logic in this code, is that the standard?

The buffers' ports are declared as std_logic because that's the most commonly-used type to represent real digital logic situations.

----------------------------Yes, I do this for a living.
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dabell-cc
Visitor
Visitor
7,982 Views
Registered: ‎01-18-2013
Thanks bassman!
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dabell-cc
Visitor
Visitor
7,974 Views
Registered: ‎01-18-2013
Oh, didn't see that.
Thanks for answering my questions mcgett!
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msh
Voyager
Voyager
3,134 Views
Registered: ‎10-31-2016

Hi, 

A additional doubt, while using the input pin for LVDS, how should I declair it in the IO planning.
I mean does IO standard column should be specified as LVDS_25 ? or normal pins ?

Thank you

Bes regards  

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gnarahar
Moderator
Moderator
3,124 Views
Registered: ‎07-23-2015

@msh Every pin should have an IO Standard. If you want to use it as LVDS differential Input pin, you need to specify LVDS_25.

 

Just FYI, always create a new thread for new queries to get quicker response and visibility 

- Giri
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