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msh
Voyager
Voyager
3,643 Views
Registered: ‎10-31-2016

LVDS output

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Hi, 

 

I have implemented a simple program 

ibrary IEEE;
use IEEE.STD_LOGIC_1164.ALL;

-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;

-- Uncomment the following library declaration if instantiating
-- any Xilinx leaf cells in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity TDC_EvaluationSignal is
    Port ( Refclk : in STD_LOGIC;
           StopSignal : out STD_LOGIC;
           TDCrefClk : out STD_LOGIC);
end TDC_EvaluationSignal;

architecture Behavioral of TDC_EvaluationSignal is

signal StopSignalReg: STD_LOGIC := '0'; 
signal TDCrefClkReg: STD_LOGIC := '0';
signal counterReg: integer := 0; 
signal TDCrefClkRegPrev : STD_LOGIC := '0';
begin

Generateclock : process (RefClk) begin
            if (RefClk= '1' and RefClk'event) then 
                TDCrefClkReg <= not TDCrefClkReg; 
                counterReg <= 1;   
                    if (counterReg =1) then 
                        counterReg <= 0;
                        StopSignalReg <= '1';
                    end if;
            end if; 
            
            if (RefClk= '0') then 
                StopSignalReg <= '0'; 
            end if;
end process; 
 
StopSignal <= StopSignalReg;
TDCrefClk <= TDCrefClkReg;
end Behavioral;

In simulation I can see the signal, but after flashing in hardware I can only see TDCrefclk not stopSignal.

further I take this signal to generate LVDS output 

Capture.PNG

 

But stil these LVDS outptu is not available at the set PINS 

here is the pin configuration 
Capture.PNG

There is a signal on Fclk and TDCcrefCk but not stop_signal. stop_signal_ p and TDCClk_p 

May I know what wrong I am doing. How can I proceed ?

thank you 
best regards 

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1 Solution

Accepted Solutions
muzaffer
Teacher
Teacher
6,595 Views
Registered: ‎03-31-2012
You have two options, one simpler and one slightly more complicated:
run the main clock at twice the speed and have stopsignal change at ever posedge & tdrefclk change at every other posedge to generate the timing you want.
If you can't run the input clock at 2x speed, you can use a DDR output cell (ODDR) for stopsignal and drive its inputs properly.
- Please mark the Answer as "Accept as solution" if information provided is helpful.
Give Kudos to a post which you think is helpful and reply oriented.

View solution in original post

5 Replies
msh
Voyager
Voyager
3,639 Views
Registered: ‎10-31-2016

Additional Information: 

 

I am testing the output on oscilloscope. 

 

Here is the schematic view of the program 
Capture.PNG

 

thank you 

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muzaffer
Teacher
Teacher
3,627 Views
Registered: ‎03-31-2012

@msh

            if (RefClk= '0') then 
                StopSignalReg <= '0'; 
            end if;

These lines are causing the trouble for you. Your description of StopSignal register does not conform to synthesizable subset. You need to change it so that you update it only on one edge of the clock. 

- Please mark the Answer as "Accept as solution" if information provided is helpful.
Give Kudos to a post which you think is helpful and reply oriented.
msh
Voyager
Voyager
3,601 Views
Registered: ‎10-31-2016

Hi @muzaffer

Thank you for pointing out the my mistake.

I would like to know if I want to initiate a signl and rising edge of clock and then want to make it zero at falling edge of the clock.
how should I proceed ?

thanks

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msh
Voyager
Voyager
3,592 Views
Registered: ‎10-31-2016

Hi, 

 

I changed the code to 

 

Generateclock : process (RefClk) begin
            if (RefClk= '1' and RefClk'event) then 
                TDCrefClkReg <= not TDCrefClkReg; 
                counterReg <= 1;   
                    if (counterReg =1) then 
                        counterReg <= 0;
                        StopSignalReg <= '1';
                        StopSignalReg <= '0' after 500ns;
                    end if;
            end if; 

still it dont work

 

May I have your suggestion what should I do to get this waveform 

 

Capture.PNG

0 Kudos
muzaffer
Teacher
Teacher
6,596 Views
Registered: ‎03-31-2012
You have two options, one simpler and one slightly more complicated:
run the main clock at twice the speed and have stopsignal change at ever posedge & tdrefclk change at every other posedge to generate the timing you want.
If you can't run the input clock at 2x speed, you can use a DDR output cell (ODDR) for stopsignal and drive its inputs properly.
- Please mark the Answer as "Accept as solution" if information provided is helpful.
Give Kudos to a post which you think is helpful and reply oriented.

View solution in original post