LogiCORE RapidIO - simulation initialization not success

[yangshiqin]

hi,

  I had used the Vivado Design suite to generate the Serial RapidIO Gen2 Endpoint.At the same time,
the SRIO Gen2 Endpoint example design has been generated.Then I used this example design to simulate,but I found
the port_initialized without success.As shown below：

How can I resolve this issue?

[balkris · Accepted solution]

Ports are defined as wires in the srio_example_top.v



In order to use them, the code must be editted and the VALIDATION_FEATURES parameter must be changed.

check these links as well
https://forums.xilinx.com/t5/Networking-and-Connectivity/SRIO-IPcore-Debug-problem/td-p/339869

http://www.xilinx.com/Attachment/Xilinx_Answer_50166_SRIO_Debugging_Packet_Analysis_Guide_ver1.pdf

[zym007432]

Have you solved the problem mentioned above?i have met the same problem with you