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yangshiqin
Visitor
Visitor
2,958 Views
Registered: ‎01-03-2016

LogiCORE RapidIO - simulation initialization not success

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hi,

  I had used the Vivado Design suite to generate the Serial RapidIO Gen2 Endpoint.At the same time,
the SRIO Gen2 Endpoint example design has been generated.Then I used this example design to simulate,but I found
the port_initialized without success.As shown below:

Image 1.png

How can I resolve this issue?

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balkris
Xilinx Employee
Xilinx Employee
5,366 Views
Registered: ‎08-01-2008
Ports are defined as wires in the srio_example_top.v



In order to use them, the code must be editted and the VALIDATION_FEATURES parameter must be changed.

check these links as well
https://forums.xilinx.com/t5/Networking-and-Connectivity/SRIO-IPcore-Debug-problem/td-p/339869

http://www.xilinx.com/Attachment/Xilinx_Answer_50166_SRIO_Debugging_Packet_Analysis_Guide_ver1.pdf
Thanks and Regards
Balkrishan
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balkris
Xilinx Employee
Xilinx Employee
5,367 Views
Registered: ‎08-01-2008
Ports are defined as wires in the srio_example_top.v



In order to use them, the code must be editted and the VALIDATION_FEATURES parameter must be changed.

check these links as well
https://forums.xilinx.com/t5/Networking-and-Connectivity/SRIO-IPcore-Debug-problem/td-p/339869

http://www.xilinx.com/Attachment/Xilinx_Answer_50166_SRIO_Debugging_Packet_Analysis_Guide_ver1.pdf
Thanks and Regards
Balkrishan
--------------------------------------------------------------------------------------------
Please mark the post as an answer "Accept as solution" in case it helped resolve your query.
Give kudos in case a post in case it guided to the solution.

View solution in original post

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zym007432
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Newbie
1,309 Views
Registered: ‎03-16-2017
Have you solved the problem mentioned above?i have met the same problem with you
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