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Anonymous
Not applicable
7,934 Views

Matlab Simulink black box sub module

Hello everybody,

 

how can I include two sub modules in the simulink xilinx black box? In the matlab configuration file I'm using the command "this_block.addFile('... .v')". My two submodules are ahead of the topmodule and all verilog files are in the same directory.

 

I can also generate the verilog code out of the simulink model with the system generator. So I can use the verilog code from my simulink model in the ISE Project Navigator. There is no problem with the correctness of the verilog modules.

 

But my problem is, that I can not run my simulink model after the including of the topmodule with the two submodules.

I'm using Matlab r2012b, Simulink Version 8.0 and ISE Project Navigator 14.5.

 

 

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8 Replies
vsrunga
Xilinx Employee
Xilinx Employee
7,929 Views
Registered: ‎07-11-2011

Hi,

 

Please refer below UG chapter -4 , this is the general flow to bring .v/.vhd files in to sysgen as a block box and simulate in system generator.

 

http://www.xilinx.com/support/documentation/sw_manuals/xilinx14_7/sysgen_ref.pdf

 


If you have followed this and still face issues please share us the error log or your hurdle so as to have more clues.

 

 

Regards,

Vanitha.

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Anonymous
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There is no problem to create the black box. The .m file shows you how I include the .v files. (Line 127 to 129). The verilog file "xl_select_controller_koordmux.v" is my topmodule.

 

The error message "Bool type output port op gets indeterminate value" is reported by another block. This block runs correct, when the black box (with two submodules) isn't included. The outputs of the black box are connected to "assert" blocks. So the types of the output are also correct.

 

So when I include the black box in my simulink model, then its impossible to run the simulation of the model. So maybe there is something wrong with the config.m file?

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vsrunga
Xilinx Employee
Xilinx Employee
7,914 Views
Registered: ‎07-11-2011

Hi,

 

A bit old but can you check this link http://www.xilinx.com/support/answers/36919.html

 

If it does not help please attach you mdl for invetisgation.

 

 

 

Regards,

Vanitha.

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eilert
Teacher
Teacher
7,912 Views
Registered: ‎08-14-2007

Hi Maximilian,

there is another common source why black boxes refuse to work.

 

In the black box properties the simulation tool is disabled by default.

So without a simulator no outputs will be generated.

Set it to ISIM at least, or configure it to use ModelSim if you have it.

 

Have a nice simulation

  Eilert

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Anonymous
Not applicable
7,878 Views

Hello eilert,

 

thank you very much for your help. I used in the properties of the black box the simulation mode: ISE Simulator. I also used cast blocks to convert the output types. But there is no change in the error message.

 

Are there any rules for the name of the verilog module? Sometime Matlab has problems, when the name of the model is wrong (or when there are numbers in the name). 

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balkris
Xilinx Employee
Xilinx Employee
7,787 Views
Registered: ‎08-01-2008

You can try with manually modify generated .m file .

The other option you can try to generate the top level wrapper and ngc file for your complete design. You can create black box using wrapper and NGC file

There are few more solutions which i got for internal database. It may applicable for you.

Solution 1

SysGen does not appear to like having a Boolean output for the Slice8 block when using the Concat4 block as the output type of the Concat4 block is set to "double".

You can work around this by opening the Slice block and deselecting the Boolean output option, and then set the Width of slice = 1 as a workaround.

Solution 2

This error has been seen to occur erroneously when using Matlab 2009a. Upgrading to Matlab 2010a or newer resolves the issue.

Solution 3

This error has been observed while running the example design "QAM System with Packet Framing and FEC for Telemetry Channels" on the following hardware/software configurations:

Windows XP 32-bit, Matlab 2010a, ISE 12.3
Windows 7 64-bit, Matlab 2009b and 2010a, ISE 12.3

However, the issue does not occur on machines with the following configurations:

Windows XP 32-bit, Matlab 2009b, ISE 12.3
Windows XP 64-bit, Matlab 2010a, ISE 12.3
Linux 64-bit, Matlab 2010a, ISE 12.3

Thanks and Regards
Balkrishan
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e_stoimenov
Visitor
Visitor
7,692 Views
Registered: ‎03-16-2011

Hi, try to set some default value of all the outputs of the blkack box. For ex:

a: out std_logic :='0';

This is working for me!
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5,708 Views
Registered: ‎03-09-2014

Thank you very much!

 

finally some helpful advise. And I dont mean the people copypasting AR contents but I'm talking about e_stoimenov that got the right hint for me, thank you.

 

Regards,

Christian

 

PS: this problem happened to me with ISE 14.7 and matlab 2013b

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