01-05-2015 12:31 AM
hai
i am using ml605 board, and i want to interface ddr3 ram with MIG, the MIG requires two clocks (200,400 MHz). so i generated from MMCM and interfaced to MIG then the error comming as the both clock lines has multiple drivers. i tried to solve by seeing other threads but its not happened. please give me solution
i tried the mmcm with and without output buffers
if i put output buffer error comming as multiple buffers in one line
if i remove buffer then error comming as line has multiple drivers
thanks...
01-05-2015 12:33 AM - edited 01-05-2015 12:38 AM
Hello,
I suggest you to check the Technology schematic when the error was multiple buffers in one line.
Then write the buffer_type constraint on that specific net.
If using ISE, see the section buffer_type in the following user guide: http://www.xilinx.com/support/documentation/sw_manuals/xilinx14_7/xst_v6s6.pdf
If using Vivado, see http://www.xilinx.com/support/documentation/sw_manuals/xilinx2014_4/ug901-vivado-synthesis.pdf
Thanks,
Vinay
01-05-2015 12:35 AM
01-05-2015 12:37 AM - edited 01-05-2015 12:42 AM
Hi,
You can use MMCM with in MIG and derive required clocks so that it save additional MMCM.
Please check below link and follow the suggestions for modifying the RTL
http://www.xilinx.com/support/answers/35242.html
http://www.xilinx.com/support/answers/43559.html
Hope this helps
-Vanitha