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Visitor
Posts: 3
Registered: ‎06-16-2017
Accepted Solution

Mutliple Related Clocks in System Generator

Hi,

 

I have a system generator design for a high-speed signal path.  I have normal gateways for the data path.  However, I also need some AXI registers for controlling various parts of the design so some of the gateways I am defining as AXI-Lite registers for control and status.  My signal path circuit is at 500MHz. The processor I am interfacing to is a microblaze and the AXI bus from the MB is running at 250MHz.  The 250MHz and 500MHz clocks are generated from the same MMCM so they are related and analyzed by the tool for timing. 

 

Is there any way to create the system generator design to provide two clocks, one for the axi access and one for the signal path but still treat the two clocks as related?  I tried to multiple-clock method within system generator.  This does provide two clocks, one for the axi and one for the signal path.  I used a register, not a fifo, for the domain crossing because the tool requires it.  However, it treats this register as an async clock domain crossing and adds four registers when viewed in the RTL viewer.  The first register is clocked by the source clock and the next three reg clocked by the destination clock.  It also adds a falsepath constraint to cut timing at this crossing.

 

Latency is critical for me, even for the axi accesses, so having these four registers is not desirable.  What I need is for system generator to treat these clocks as related and only add a single register at the cross between 250 and 500 and to analyze the timing since the clocks are generated by the same MCMM.

 

Thanks in advance for help.

-Chris


Accepted Solutions
Visitor
Posts: 3
Registered: ‎06-16-2017

Re: Mutliple Related Clocks in System Generator

I implemented it as you suggested with the full design running at 500MHz including the axi.  I checked to see what was implemented in the AXI switch.  It automatically detected that the clocks are related and did not add a FIFO.  So it appears that IPI is smart or at least smarter than SYSGEN.  It also met timing for a small design so this is probably the way to go.  

Thanks  

Chris

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Xilinx Employee
Posts: 3,596
Registered: ‎08-02-2011

Re: Mutliple Related Clocks in System Generator

[ Edited ]

Hi Chris,

 

Yeah, the 'Multiple Async Clocks' option is only for truly async clocks.

 

I'd do the clock crossing in the AXI Interconnect before the sysgen control. In other words, the MI slot on the AXI Interconnect that the sysgen block connects to should be at 500MHz (but the rest of the clocks on that interconnect for the rest of the processor system are at 250MHz).

 

That way, everything in sysgen land will neatly be on one clock at 500 and Vivado should know enough about the relation of the two clocks to handle it properly in the interconnect.

 

www.xilinx.com
Visitor
Posts: 3
Registered: ‎06-16-2017

Re: Mutliple Related Clocks in System Generator

Hi bwiec,

 

Thanks for the reply and for confirming that "Mult Clock" is really for async clocks.  It would be nice if there was a switch in the tool that would allow me to tell it that they are sync clocks.  

 

I thought about what you suggested but I was concerned about running the AXI-LITE interfaces at 500MHz and being able to close timing.  I am also concerned that if I operate the AXI switch for that port at 500MHz and the others at 250, it would still treat them as async and add the CDC FIFOs, etc.... to the switch unnecessarily.

 

I will give it a try and see how timing looks. 

 

Best regards,

Chris

 

 

 

Visitor
Posts: 3
Registered: ‎06-16-2017

Re: Mutliple Related Clocks in System Generator

I implemented it as you suggested with the full design running at 500MHz including the axi.  I checked to see what was implemented in the AXI switch.  It automatically detected that the clocks are related and did not add a FIFO.  So it appears that IPI is smart or at least smarter than SYSGEN.  It also met timing for a small design so this is probably the way to go.  

Thanks  

Chris