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Visitor jigarmori
Visitor
1,685 Views
Registered: ‎04-04-2013

Nexys4 DDR H/W Co-Simulation

Hi,

 

I am working on Nexys4 DDR (Artix 7) using Xilinx ISE 14.2. 
I could run my basic LED program using ISE.

 

Now, I have created plugins for hardware co simulation and when I am generating bit file I am facing issue of constraint. I am using correct ucf. I can bypass this error but then my program is not running on hardware. I have 

 

ERROR:Bitgen:342 - This design contains pins which have locations (LOC) that are
not user-assigned or I/O Standards (IOSTANDARD) that are not user-assigned.
This may cause I/O contention or incompatibility with the board power or
connectivity affecting performance, signal integrity or in extreme cases
cause damage to the device or the components to which it is connected. To
prevent this error, it is highly suggested to specify all pin locations and
I/O standards to avoid potential contention or conflicts and allow proper
bitstream creation. To demote this error to a warning and allow bitstream
creation with unspecified I/O location or standards, you may apply the
following bitgen switch: -g UnconstrainedPins:Allow

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