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Newbie
Newbie
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Registered: ‎07-11-2017

NgdBuild:478 - clock net rst_inv_BUFG with clock driver rst_inv_BUFG drives no clock pins, FPGA testing fail

Hi,  I am generating my bit file after designing my verilog code, and want to program this bit file to FPGA to test my circuit.

The tools I use : 

 

Xilinx Design Suite 14.7

Virtex7 690T , package 1157, speed -3

 

The Translation report has a warning ( no error ):

NgdBuild:478 - clock net rst_inv_BUFG with clock driver rst_inv_BUFG  drives no clock pins

 

Map report and P&R report show no error or warning.

 

 

I really have a input signal named rst, and used for synchronous reseting.

I am having searching for this issue but can not get answer to me.
And now I ignore this warning and program bit file to FPGA and do testing, however I can not get any output signal ( I ensure that I input right data signal at right timing )

Is this warning reason for testing fail? If yes, how can I get this warning fixed.
Please help , thank you!!

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