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naveengk14
Explorer
Explorer
3,251 Views
Registered: ‎09-16-2013

Post synthesis

Hi,

 

utilization after Post synthesis  is nothing but Utilization after Implementations ..?

Thanks
Naveen G K
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syedz
Moderator
Moderator
3,247 Views
Registered: ‎01-16-2013

@naveengk14,

 

Can you please share the utilization report?

I suspect that design has dcp or netlist files which will be considered as black box during synthesis. Hence you wont see the accurate/correct numbers.

 

The utilization will be correct in post implementation reports.

 

--Syed

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svanapar
Explorer
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Registered: ‎11-25-2015

@naveengk14

 

Refer https://forums.xilinx.com/t5/Implementation/Vivado-2013-4-utilization-reports/td-p/475408 for more explanation on synthesis utilization report.

 

Regards,

Sravanthi

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saradapr
Explorer
Explorer
3,178 Views
Registered: ‎10-14-2015

Hi @naveengk14,

 

Hope below link helps.

 

https://forums.xilinx.com/t5/Implementation/Different-logic-utilization-after-synthesis-and-implementation/td-p/597343

 

Thanks,

Sarada

 

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muzaffer
Teacher
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3,166 Views
Registered: ‎03-31-2012

@naveengk14

>> utilization after Post synthesis is nothing but Utilization after Implementations ..?

your question is not very clear. Do you mean utilization post synthesis is zero ? Or are you asking if it is the same value as after implementation ?

If former, there might be blocks which are not included in your report because they're not fully implemented yet but it still shouldn't be zero.
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athandr
Xilinx Employee
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Registered: ‎07-31-2012

If your question is if these are same or different, then the answer is No, the utilization post synthesis and after implementation are different. Post synthesis utilzation is just an estimate, the actual utilization is when the logic is put on the FPGA and this is the correct indication of your resource utilization.
Thanks,
Anirudh

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