UPGRADE YOUR BROWSER

We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

cancel
Showing results for 
Search instead for 
Did you mean: 
Highlighted
Visitor sombresleep
Visitor
2,862 Views
Registered: ‎11-18-2014

Problem with AXI-PCIe core implementation in Vivado 2014.4 (Rule violation)

I am working with zc706 board and Vivado 2014.4. When I create my project around "AXI Memory Mapped To PCI Express 2.5" core or update XAPP1171 example design, I get the following behavior:

 

For the first time synthesis and implementation work. And I can program the FPGA without any problem (if the design was correct). But if I start an implementation second time (even without changing anything) it crashes with this error.

 

[Drc 23-20] Rule violation (PDRC-29) MMCM_adv_ClkFrequency_clkin1 - The calculated frequency value, 0.000 MHz, of the CLKIN1_PERIOD attribute on the MMCME2_ADV site MMCME2_ADV_X0Y2 (cell design_1_i/axi_pcie_0/U0/comp_axi_enhanced_pcie/comp_enhanced_core_top_wrap/axi_pcie_enhanced_core_top_i/pcie_7x_v2_0_2_inst/pcie_top_with_gt_top.gt_ges.gt_top_i/pipe_wrapper_i/pipe_clock_int.pipe_clock_i/mmcm_i) is outside the allowed range (10.000 - 933.000 MHz). Please change the CLKIN1_PERIOD attribute value in order to be within the allowed range for this device.

 

I have no idea how to eliminate this error.

0 Kudos
4 Replies
Xilinx Employee
Xilinx Employee
2,854 Views
Registered: ‎07-11-2011

Re: Problem with AXI-PCIe core implementation in Vivado 2014.4 (Rule violation)

Hi,

 

Did you use any Debug cores?

 

Can you try by appying don't touch attribute to your MMCM  instance ?

 

example:-

set_property DONT_TOUCH TRUE [get_cells gcGTP_USED_LANES_4.gtp_stream_wrapper/tx_4_inst/i_multiline/U0/gt_usrclk_source/txoutclk_mmcm0_i/mmcm_adv_inst]

 

Hope this helps

 

-Vanitha

---------------------------------------------------------------------------------------------
Please do google search before posting, you may find relavant information.
Mark the post - "Accept as solution" and give kudos if information provided is helpful and reply oriented
0 Kudos
Visitor sombresleep
Visitor
2,836 Views
Registered: ‎11-18-2014

Re: Problem with AXI-PCIe core implementation in Vivado 2014.4 (Rule violation)

It didn't help.

 

I used debug cores before but now I did a pure experiment. I created a new project without any debug cores, added DONT_TOUCH to mmcm_i net and synthesized the design. Then the bitstream was uploaded to my FPGA. The design worked perfectly. 

I started synthesis and then implementation without making any changes (at all). That error came up again.

 

 

0 Kudos
Xilinx Employee
Xilinx Employee
2,833 Views
Registered: ‎07-11-2011

Re: Problem with AXI-PCIe core implementation in Vivado 2014.4 (Rule violation)

Hi,

 

I have come across similar erro in other IP due to rounding error in time period calculations in Vivado,  which is scheduled for fix in future vivado release and can be seen in specific clocking configurations.

I am not sure if this applie to this as well, but the  work around was to increase/decrease the clock period in error message by 1ps in applicable places,  like XDC and top level RTL files.

Please check if that helps

 

- Vanitha

---------------------------------------------------------------------------------------------
Please do google search before posting, you may find relavant information.
Mark the post - "Accept as solution" and give kudos if information provided is helpful and reply oriented
0 Kudos
Visitor sombresleep
Visitor
2,819 Views
Registered: ‎11-18-2014

Re: Problem with AXI-PCIe core implementation in Vivado 2014.4 (Rule violation)

Ok I think I came up with the solution.

 

That CLKIN1_PERIOD attribute depends on REFCLK parameter which comes directly from the IP settings. The error doesn't show up If I open the IP settings dialogue box (in IP integrator), change the frequency to something random, then change it back to my value and save it.

 

 

This is it. I have to do it every time before the synthesis, but it is not a big problem actually.

 

 

 

0 Kudos