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Visitor oscarseijo
Visitor
2,505 Views
Registered: ‎12-12-2014

RAM SPEED?

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Hello everyone, i am currently doing my final degree project and I need to use an FPGA. My project is basically a digital beamforming reciever, with four 60 Mega samples/s 10-bits ADCs, so i have a 60MHz clock speed for the FPGA and the ADCs. This makes a total of 600 Mbps dataspeed for each of the ADCs.

 

Just after the ADCs, in the FPGA, i have to use a memory (RAM) to store aprox 50 samples for each of the ADCs (500 bits) and delay them. Here is my problem, I have to read and write at different memory positions at the same time with that speed. 

 

Will A low-end FPGA such as the Spartan 6 XC6SLX9 FPGA be enough to achieve this data speed? Which time of memory should i use? 

  If not, Any Ideas? 

 

Thank you very much for your attention.

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Instructor
Instructor
3,525 Views
Registered: ‎08-14-2007

Re: RAM SPEED?

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1)  Block RAM and Distributed RAM use different physical resources so you can have both.  However Distributed RAM uses up LUT resources, so if you use the maximum shown in the data sheet you will eat up a lot of your logic fabric.

 

2) Either RAM type allows you to read two addresses at once.  BRAM also allows you to write at two addresses at once, but you only get two addresses total.  That means you can write one address and read another simultaneously, or write two locations simultaneously while reading the previous value of those same two locations for example.  Distributed RAM has only one write port.

 

It sounds like you should easily be able to do what you want in the LX9.  I would suggest to make sure your memory requirement can be fully addressed in BRAM, though.  That gives you the maximum amount of logic resources for your filtering.

 

Your best approach is to actually make the design and run through the tools (ISE).  That will tell you if it will fit in the part and meet timing.  By the way, 60 MHz is considered quite slow in Spartan 6.  You could bump that up by a factor of 4 and reduce logic usage by taking 4 clock cycles to process each input sample.  Among other things that would give you the opportunity to read up to 8 locations of each BRAM during one sample period.  However if you don't have the time to do the design before ordering hardware, I still think it's a safe bet that the LX9 will fit the bill.

-- Gabor
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Scholar muravin
Scholar
2,491 Views
Registered: ‎11-21-2013

Re: RAM SPEED?

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I believe you should be fine with XC6SLX9 unless you are planning to use some crazy post-data acquisition DSP function that would exhaust the FPGA resources.
Cheers Vlad
Vladislav Muravin
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Visitor oscarseijo
Visitor
2,479 Views
Registered: ‎12-12-2014

Re: RAM SPEED?

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What about the RAM? I dont really understand the difference between block and distributed. Can I use both for my application? Both can be read and written at the same time? On the other hand it was impossible to find any information about the RAM speed, I only found 'fast block RAM, fast distributed RAM. But how fast? haha. I believe you if you say its fast enough.

 

I only want to use the FPGA as a reciever, add the four signals into one signal, mix the result and FIR filtering after the mixing. The diveristy processing will be made in a microcontroller. out of the FPGA board.

 

Thank you very much for your attention, really :D

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Instructor
Instructor
3,526 Views
Registered: ‎08-14-2007

Re: RAM SPEED?

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1)  Block RAM and Distributed RAM use different physical resources so you can have both.  However Distributed RAM uses up LUT resources, so if you use the maximum shown in the data sheet you will eat up a lot of your logic fabric.

 

2) Either RAM type allows you to read two addresses at once.  BRAM also allows you to write at two addresses at once, but you only get two addresses total.  That means you can write one address and read another simultaneously, or write two locations simultaneously while reading the previous value of those same two locations for example.  Distributed RAM has only one write port.

 

It sounds like you should easily be able to do what you want in the LX9.  I would suggest to make sure your memory requirement can be fully addressed in BRAM, though.  That gives you the maximum amount of logic resources for your filtering.

 

Your best approach is to actually make the design and run through the tools (ISE).  That will tell you if it will fit in the part and meet timing.  By the way, 60 MHz is considered quite slow in Spartan 6.  You could bump that up by a factor of 4 and reduce logic usage by taking 4 clock cycles to process each input sample.  Among other things that would give you the opportunity to read up to 8 locations of each BRAM during one sample period.  However if you don't have the time to do the design before ordering hardware, I still think it's a safe bet that the LX9 will fit the bill.

-- Gabor
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Visitor oscarseijo
Visitor
2,458 Views
Registered: ‎12-12-2014

Re: RAM SPEED?

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Awesome answers and really quick, thank you very much. I made the reciever simulations more or less and it fits on the LX9 so Perfect! I have 3-4 months to do the complete design including an app to recieve the data in my pc and the external microcontroller programming, so I will continue with a 60 MHz clock I think.

 

Again, thank you very much. :-)

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