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lucio_
Visitor
Visitor
4,831 Views
Registered: ‎10-14-2015

Spartan 6 SPI Flash programming

Hi,

 

I am using spartan 6 XC6SLX9 and M25P40 flash memory.

 

For direct SPI programming I don't use PROGRAM_B, but just MOSI, MISO, CS and CCLK. Is this OK ?

 

PROGRAM_B is used to force these pins (from FPGA side) to High Impedance, but is there any possibility to have them in High or Low state if I don't use PROGRAM_B ?

 

I can set them to High-Z from VHDL code but, for example, what does it happen after configuration with a blank flash memory ?

 

Thanks, best regards,

Lucio

 

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trenz-al
Scholar
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Registered: ‎11-09-2013

with blank memory the FPGA will set SPI as master and try forever and you can not access the spi from your spi direct programmer..

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gszakacs
Professor
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Registered: ‎08-14-2007


@trenz-al wrote:

with blank memory the FPGA will set SPI as master and try forever and you can not access the spi from your spi direct programmer..


Actually that depends on the mode pins.  I you can change the programming mode to any slave configuration mode, then the FPGA should not be driving the pins.  Still that requires at least some connections other than the SPI connections, so in effect you might as well use PROGRAM_B.

-- Gabor
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lucio_
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Registered: ‎10-14-2015

FPGA is MASTER (M0 = High, M1 = Low).

 

In this case what does it happen with blank memory ?

 

Could you link me to some dovumentation ?

 

Thanks,

 

Lucio

 

 

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gszakacs
Professor
Professor
4,727 Views
Registered: ‎08-14-2007

It would be best to try an experiment to test this, but it looks like the Spartan 6 will eventually give up if the flash is blank because it won't get a sync word.  See the flow diagram on page 44 of ug380.  Typically a blank flash will output all 1's.  The flow diagram implies that the FPGA will first issue opcode 3 and issue up to 512 clocks looking for the sync word.  If that fails it will try again with opcode E8 and again issue up to 512 clocks.  If that fails, the process starts over and runs the whole thing 3 more times.  So you can expect at least 4096 clocks plus the command time, all running at the slowest internal CCLK rate (CCLK only bumps up when the first part of the bitstream changes it).  After that, initialization fails and (presumably) the part will tristate the SPI connections.

 

My experience with earlier FPGA families from Xilinx was different.  In earlier devices, the CCLK would run continuously as noted by trenz_al.  I don't remember ever looking at this on a Spartan 6 design, which is why I'd suggest doing an experiment before you go ahead and build a board without the PROGRAM_B connection for direct SPI programming.  Of course there are other problems with leaving out the PROGRAM_B connection.  For example you could have a flash programmed with a bitstream that drives the SPI connections.  Then you'd have a problem trying to erase it, unless you also had a JTAG cable to load something else into the FPGA.

-- Gabor
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