12-11-2015 04:06 AM
I am developing the hardware for one of our XMC cards that uses a Spartan-6 LX45T.
I have little experience with VHDL in general, so all I am doing is qualifying the PCIe link before handing the hardware over to an external developer.
I am generating the PCIe core (Version 2.4) using ISE 14.7 and then running the implement.bat found in the coregen directory.
When I generate the core I am leaving all the settings as standard, except I am changing the clock to 125 MHz since that is what is present.
I am also editing the .ucf file to select the correct system_resetn pin (V20 in this case).
Once I generate the routed.bit file, I upload this to the card and soft reset the PC so the config file is not lost.
I am running Mint (Linux version 3.5.0-17) and then using the lspci command to see if the card is present in the PCI config space.
So to the punch, I am not able to see the card come up at all using the lspci command.
I have done this process a couple of times changing a few settings, but to no avail.
I am specifically using the Avnet Spartan-6 LX16 Evaluation Kit (http://www.xilinx.com/products/boards_kits/spartan6.htm) which I have tested successfully using an example IP core (generated .bit file) from Norwest Logic (http://nwlogic.com/products/development-boards) so I know the PC and card works to a degree.
Our XMC adapter uses the Spartan-6 LX45T which is designed in a very similar way to the Avnet Spartan-6 LX16 Evaluation Kit (PCIe x4 lane while the example design is limited to 1 lane).
Am I misunderstanding how the PCIe core and PIO example works?
Is using the lspci command enough to see the PIO example design?
What could I be missing?
Thanks in advance
12-15-2015 09:02 AM
@kortel, please go through below Xilinx AR and follow the debug steps to root cause the failure.
If in case you see link failure visit below link
Hope this helps