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Highlighted
4,830 Views
Registered: ‎06-06-2016

Syntax error [8-999] and [17-69]

Hello there,

 

I was making a test in school and our teacher gave us this code to make a frequence divider.

 

51.Process(CLK)
52.    variable count : STD_LOGIC_VECTOR(24 downto 0);
53.begin
54. if CLK'event and clk='1' then
55.  count := count + 1;
56.end if;
57.if count = "1011111010111100001000000" then
58.  Puls <= '1';
59.  count := "0000000000000000000000000";
60.else
61.  Puls <= '0';
62.end if;
63.end process;

 

with this code i got these errors:

 

[Common 17-69] Command failed: Synthesis failed - please see the console or run log file for details

[Synth 8-944] 0 definitions of operator "+" match here [EVA2.vhd 55]

 

 

I have been looking on this forum to solve the problem but those solutions did not help. I do have

 use IEEE.NUMERIC_STD.ALL; enabled. so i don't know what i can still do to solve this.

 

Friendly greets.

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Highlighted
Scholar
Scholar
4,812 Views
Registered: ‎02-27-2008

c,

 

http://www.seas.upenn.edu/~ese171/vhdl/vhdl_primer.html#_Toc526061343

 

Lots of resources and examples of how to write VHDL.  The above is just one of many.  Start at the beginning.

Austin Lesea
Principal Engineer
Xilinx San Jose
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