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Visitor gbosque
Visitor
8,182 Views
Registered: ‎01-15-2015

System Generator - DCM in a project - error generating bitstream or hw-in-the-loop

Hellow,

 

I am generating several examples for the students but I have met  with the problem below mentioned.

 

Working on ISE:

1. I have a design of a counter up-down with a DCM. The design works well when are generated on ISE 14.5 and programmed on a Spartan-3E.

 

Working on Simulink-System generator

1. When I work with de design on a Black-Box an simulate, works correctly.

2. If I try to generate a bitstream or a HW-in-the-loop, the error is the next:

 

Xst:2035 - Port <clk> has illegal connections. This port is connected to an input buffer and other components.

 

Thanks

 

Guillermo

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3 Replies
Xilinx Employee
Xilinx Employee
8,176 Views
Registered: ‎08-01-2008

Re: System Generator - DCM in a project - error generating bitstream or hw-in-the-loop

check Hybrid DCM-CE Support option in sysgen user guide
Thanks and Regards
Balkrishan
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Xilinx Employee
Xilinx Employee
8,174 Views
Registered: ‎08-01-2008

Re: System Generator - DCM in a project - error generating bitstream or hw-in-the-loop

its not supported the way you are doing for black box
Thanks and Regards
Balkrishan
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Visitor gbosque
Visitor
8,156 Views
Registered: ‎01-15-2015

Re: System Generator - DCM in a project - error generating bitstream or hw-in-the-loop

If I understand, I can not work with dcm in system generator?

Should I work with multirate?

 

Thanks.

 

Guillermo

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